代码搜索：1Hz
找到约 197 项符合「1Hz」的源代码
代码结果 197
www.eeworm.com/read/273079/10928466
bak counter100.vhd.bak
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity CNT100 is
port(
CLKK : IN STD_LOGIC; -- 1Hz
CLK : IN STD_LOGIC;
cout : out STD_LOGIC;
led7s0,
www.eeworm.com/read/273079/10928544
vhd counter100.vhd
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity CNT100 is
port(
CLKK : IN STD_LOGIC; -- 1Hz
CLK : IN STD_LOGIC;
cout : out STD_LOGIC;
led7s0,
www.eeworm.com/read/248077/4471033
m clex95dt.m
% CLEX95DT.M Create data for processing
% for Example 9.5 in file CLEX95.MAT
% Result has Resolution= 1/NTs= 1Hz; Valid Range is to 64Hz
% (There will be symmetry about 64Hz ie at 64+(64-20)=108H
www.eeworm.com/read/188694/8519260
txt rayleigh.m.txt
% clear all variables
clear;
sig_num = 300;
fd = 1;
fs = 7;
N = 64;
fm = 10; %unit: 1Hz
Rs = 1; %unit: 1MHz
Ts = 1/Rs;
% generate random QPSK signal
qpsk_D=randint(sig_num,1,4);
qpsk_
www.eeworm.com/read/178544/9392227
m rayleigh.m
% clear all variables
clear;
sig_num = 300;
fd = 1;
fs = 7;
N = 64;
fm = 10; %unit: 1Hz
Rs = 1; %unit: 1MHz
Ts = 1/Rs;
% generate random QPSK signal
qpsk_D=randint(sig_num,1,4);
qpsk_
www.eeworm.com/read/174563/9581609
m rayleigh.m
% clear all variables
clear;
sig_num = 300;
fd = 1;
fs = 7;
N = 64;
fm = 10; %unit: 1Hz
Rs = 1; %unit: 1MHz
Ts = 1/Rs;
% generate random QPSK signal
qpsk_D=randint(sig_num,1,4);
qpsk_
www.eeworm.com/read/166859/9993221
vhd count10.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity count10 is
port( clk:in std_logic; --1hz
en:in std_logic;
clr:in std_logic;
up
www.eeworm.com/read/353706/10428842
vhd ftctrl.vhd
LIBRARY IEEE; --测控控制电路
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FTCTRL IS
PORT (CLKK : IN STD_LOGIC; --1Hz
CNT_EN : OUT STD_LOGIC; --计数器时钟使能
RST
www.eeworm.com/read/448916/7522447
vhd procontrol.vhd
library ieee;
use ieee.std_logic_1164.all;
entity procontrol is
port(clk:in std_logic; --1hz的测频率控制时钟
en:out std_logic; --计数使能端
load:out std_logic; --计数器清零
clr:ou
www.eeworm.com/read/435556/7790458
vhd fq_divider.vhd
--------60分频，clkin=1HZ,clkout为1S---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fq_divider is
port(clk:in std_logic;
clkout:out std_logic);
end ent