fq_divider.vhd

来自「软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 」· VHDL 代码 · 共 30 行

--------60分频，clkin=1HZ,clkout为1S---------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fq_divider is
port(clk:in std_logic;
	clkout:out std_logic);
end entity fq_divider;
architecture one of fq_divider is
signal s:std_logic_vector(5 downto 0);
signal full:std_logic;
begin
p1:process(clk)---30分频---
begin
if clk'event and clk='1' then
	if s="011101" then s<="000000";full<='1';
	else s<=s+1;full<='0';
	end if;
end if;
end process p1;
p2:process(full)----2分频----
variable cnt2:std_logic;
begin
	if full'event and full='1' then cnt2:=not cnt2;
		if cnt2='1' then clkout<='1';
		else clkout<='0';
		end if;
	end if;
end process p2;
end architecture one;