procontrol.vhd

来自「本程序完整的实现了数字频率计的常用功能。并对通常数字频率计的常见问题进行了改进。」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;
entity procontrol is
  port(clk:in std_logic;    --1hz的测频率控制时钟
       en:out std_logic;    --计数使能端   
       load:out std_logic;  --计数器清零
       clr:out std_logic);  --输出锁存信号
end entity;
architecture art of procontrol is
  signal tem:std_logic;
  begin
  en<=tem;
  load<=not tem;

-----------------------
  process(clk)is
    begin
     if(rising_edge(clk)) then
       tem<=not tem;
     end if;
  end process;
-----------------------
  process(clk,tem)
    begin
      if(clk='0' and tem='0') then
        clr<='1';
      else clr<='0';
      end if;
  end process;
end art;