counter100.vhd.bak

基于VHDL的8位十进制频率计的详细设计。

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_unsigned.all;
entity CNT100 is
	 port(
		 CLKK : IN STD_LOGIC;  -- 1Hz
		 CLK  : IN STD_LOGIC;
		 cout : out STD_LOGIC;
		 led7s0,led7s1 : out STD_LOGIC_VECTOR(6 downto 0)
	     );
end CNT100;
architecture CNT100 of CNT100 is
signal DIV2CLK,CNT_EN,RST_CNT : STD_LOGIC;
signal q_tmp :STD_LOGIC_VECTOR(7 downto 0);
signal q_bcd :STD_LOGIC_VECTOR(7 downto 0);
signal q_bcd_low,q_bcd_high:STD_LOGIC_VECTOR(3 downto 0);
begin
PP:   PROCESS( CLKK )
    BEGIN
      IF CLKK'EVENT AND CLKK = '1' THEN  DIV2CLK <= NOT DIV2CLK;
     END IF;
    END PROCESS;
    PROCESS (CLKK, DIV2CLK)
    BEGIN
        IF CLKK='0' AND Div2CLK='0' THEN  RST_CNT <= '1';
        ELSE  RST_CNT <= '0';   
		END IF;
    END PROCESS;
    CNT_EN <= DIV2CLK;
pe:	process(CLK,RST_CNT,CNT_EN)
	begin
		if RST_CNT='1' then 
		q_tmp<=(others=>'0');	
		elsif CLK'event and CLK='1' then
			if CNT_EN='1' then
				if 	q_tmp=99 then
				  q_tmp<=(others=>'0');
				else
			      q_tmp<=q_tmp+1;
				end if;
			end if;
		end if;
	end process;
cout <= q_tmp(0) AND q_tmp(1) AND q_tmp(5) AND q_tmp(6);
q_bcd_low<=q_bcd(3 downto 0);
q_bcd_high<=q_bcd(7 downto 4);
P1: process(q_tmp)
begin
	if q_tmp<=9 then
		q_bcd<=q_tmp;
	elsif q_tmp<=19 then
		q_bcd<=q_tmp+6;
	elsif q_tmp<=29 then
		q_bcd<=q_tmp+12;
	elsif q_tmp<=39 then
		q_bcd<=q_tmp+18;
	elsif q_tmp<=49 then
		q_bcd<=q_tmp+24;
	elsif q_tmp<=59 then
		q_bcd<=q_tmp+30;
	elsif q_tmp<=69 then
		q_bcd<=q_tmp+36;
	elsif q_tmp<=79 then
		q_bcd<=q_tmp+42;
	elsif q_tmp<=89 then
		q_bcd<=q_tmp+48;
	elsif q_tmp<=99 then
		q_bcd<=q_tmp+54;
	else
		q_bcd<=q_tmp;
	end if;
end process;
P2: process(q_bcd_low)
begin
	case q_bcd_low  is
		when "0000" =>led7s0<="0111111";
		when "0001" =>led7s0<="0000110";
		when "0010" =>led7s0<="1011011";
		when "0011" =>led7s0<="1001111";
		when "0100" =>led7s0<="1100110";
		when "0101" =>led7s0<="1101101";
		when "0110" =>led7s0<="1111101";
		when "0111" =>led7s0<="0000111";
		when "1000" =>led7s0<="1111111";
		when "1001" =>led7s0<="1101111";
		when "1010" =>led7s0<="1110111";
		when "1011" =>led7s0<="1111100";
		when "1100" =>led7s0<="0111001";
		when "1101" =>led7s0<="1011110";
		when "1110" =>led7s0<="1111001";
		when "1111" =>led7s0<="1110001";
		end case;
end process;
P3: process(q_bcd_high)
begin
	case q_bcd_high  is
		when "0000" =>led7s1<="0111111";
		when "0001" =>led7s1<="0000110";
		when "0010" =>led7s1<="1011011";
		when "0011" =>led7s1<="1001111";
		when "0100" =>led7s1<="1100110";
		when "0101" =>led7s1<="1101101";
		when "0110" =>led7s1<="1111101";
		when "0111" =>led7s1<="0000111";
		when "1000" =>led7s1<="1111111";
		when "1001" =>led7s1<="1101111";
		when "1010" =>led7s1<="1110111";
		when "1011" =>led7s1<="1111100";
		when "1100" =>led7s1<="0111001";
		when "1101" =>led7s1<="1011110";
		when "1110" =>led7s1<="1111001";
		when "1111" =>led7s1<="1110001";
		end case;
end process;
end CNT100;