代码搜索：废墨清零
找到约 859 项符合「废墨清零」的源代码
代码结果 859
www.eeworm.com/read/333698/12664629
m plotdigitpats.m
% 捞 胶农赋飘甫 龋免茄 饶, 阿 侨伎捞 沥规屈捞 登档废 扩档快 芒阑 炼沥窍矫夸
colormap('gray');
pat = zeros(6,5);
for patNum = 1:nPats,
pat(1:5,1:4) = reshape(input(:,patNum),4,5)';
axis off, subplot(10,4,patNum), pcolor(pat);
www.eeworm.com/read/306178/3756053
c jinzhihe.c
//Room: /d/dali/jinzhihe.c
//Date: June. 29 1998 by Java
inherit ROOM;
void create()
{
set("short","金汁河畔");
set("long",@LONG
这里位处金汁河畔，原本建有一座地藏寺，如今寺院早废。唯有一座
石刻经幢(jingzhuang)半埋土中。此幢为方锥状，七层石雕
www.eeworm.com/read/306178/3760070
c wuqidian.c
// Room: /u/diabio/feitian/feitian/wuqidian.c
inherit ROOM;
void create()
{
set ("short", "武器店");
set ("long", @LONG
明治时期曾经很热闹的武器店,不过维新时期过后实行了废刀令.
这里也只好关门了,武器店里面一个人也没有静悄悄的.
LONG);
s
www.eeworm.com/read/105929/15653927
htm 009.htm
书路--中国官场学
中国官场学
[学治说赘]
说赘
说具于前，已不直善为治者一噱矣。比来威友急公报国多以牧令自效，下问致
治之方，老病昏废，更无新得。且
www.eeworm.com/read/282462/9092564
vhd minsecond.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINSECOND-a is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
www.eeworm.com/read/164302/10118762
vhd fraq.vhd
library ieee;--十进制计数器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk: in std_logic;--时钟信号
clr: in std_logic;--清零信号
ena: in std_logic;--使能信
www.eeworm.com/read/164302/10118917
vhd cnt10.vhd
library ieee;--十进制计数器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
port(clk: in std_logic;--时钟信号
clr: in std_logic;--清零信号
ena: in std_logic;--使能信
www.eeworm.com/read/455332/7373238
vhd minsecond.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINSECOND-a is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
www.eeworm.com/read/321127/13411834
c romserch.c
#include "DS18B20.h"
//Rev CRC8 register
//需要在使用前由调用它的程序将其清零
unsigned char revCRC8;
//temp memory of 18B20 ROM data, using for search command
//the last two byte contains the search infomat
www.eeworm.com/read/310945/13639629
vhd add_fcw.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--频率字累加器
entity add_fcw is
port(clr:in std_logic;--清零复位,0为复位
clk:in std_logic;--
fcw:in std_logic_vector(7