fraq.vhd

基于VHDL语言的频率计具有高速计频

library ieee;--十进制计数器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
  port(clk: in std_logic;--时钟信号
       clr: in std_logic;--清零信号
       ena: in std_logic;--使能信号
       --cq:out integer range 0 to 15;
        cq: out std_logic_vector(3 downto 0);
       --cq: in std_logic_vector(3 downto 0);--计数输出
       carry_out: out std_logic);--进位
end entity cnt10;
architecture art of cnt10 is
--signal cqi:integer range 0 to 15;
signal cqi: std_logic_vector(3 downto 0);
begin
process(clk,clr,ena)
begin
if  clr='1' then cqi<="0000";
 elsif clk'event and clk='1' then
  if  ena='1' then 
   --cqi<=cqi+1;
   if cqi<9 then cqi<=cqi+1;
   else cqi<="0000";
   --if cqi="1001" then cqi="0000";
   --else cqi=cqi+1;
   end if;
 end if;
--end if; 
end if;
end process;
process(cqi) is
begin
if cqi=9 then carry_out<='1';
else carry_out<='0';
end if;
end process;
cq<=cqi;
end architecture art;

library ieee;--锁存器
use ieee.std_logic_1164.all;
entity reg32b is
  port(load: in std_logic;
        din: in std_logic_vector(31 downto 0);
        dout: out std_logic_vector(31 downto 0));
end entity reg32b;
architecture be of reg32b is
begin
process(load,din)
begin
if load'event and load='1' then
 dout<=din;
end if;
end process;
end architecture be;


library ieee;--分频
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity oscdiv is
   port(cp:in std_logic;
        result: out std_logic
        );
end entity oscdiv;
architecture fr of oscdiv is
signal rst: std_logic;
signal qn: std_logic_vector(21 downto 0);
begin 
   process(cp,rst)
  begin
     if rst='1' then
         qn<="0000000000000000000000";
     elsif cp'event and cp='1' then 
         qn<=qn+1;
     end if;
   end process;
   rst<='1' when qn=40000000 else
      '0';
  result<=qn(21);
end fr;

library ieee;--测频控制信号发生器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity testctl is
  port(clk:in std_logic;
      tsten: out std_logic;
      clr_cnt: out std_logic;
      load: out std_logic);
end entity testctl;
architecture bev of testctl is
   signal div2clk: std_logic;
   begin
   process(clk) is
   begin
    if clk'event and clk='1' then
    div2clk<=not div2clk;
    end if;
   end process;
   process(clk,div2clk) is
   begin
     if clk='0' and div2clk='0' then
     clr_cnt<='1';
     else clr_cnt<='0';
     end if;
   end process;
   load<=not div2clk;
   tsten<=div2clk;
 end architecture bev; 

library ieee;--显示控制
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity dispscan is
    port(d_in:in std_logic_vector(31 downto 0);
         reset: in std_logic;--显示重设
         clkdsp:in std_logic;--数码管显示时钟信号
         sel:out std_logic_vector(2 downto 0);--数码管选择
         d_out:out std_logic_vector(3 downto 0));
end entity dispscan;
architecture scan of dispscan is
signal sell: std_logic_vector(2 downto 0);
begin
process(clkdsp,reset,sell)
begin
if reset='0' then
  sel<="000";
  d_out<="0000";
  sell<="000";
else
  if(clkdsp'event and clkdsp='1') then
     if sell<7 then
      sell<=sell+1;
     else 
      sell<="000";
     end if;
   end if;
sel<=sell;
case sell is
   when "000"=>d_out(3)<=d_in(31); 
               d_out(2)<=d_in(30);
               d_out(1)<=d_in(29);
               d_out(0)<=d_in(28);
    when "001"=>d_out(3)<=d_in(27); 
               d_out(2)<=d_in(26);
               d_out(1)<=d_in(25);
               d_out(0)<=d_in(24);
     when "010"=>d_out(3)<=d_in(23); 
               d_out(2)<=d_in(22);
               d_out(1)<=d_in(21);
               d_out(0)<=d_in(20);
     when "011"=>d_out(3)<=d_in(19); 
               d_out(2)<=d_in(18);
               d_out(1)<=d_in(17);
               d_out(0)<=d_in(16);
     when "100"=>d_out(3)<=d_in(15); 
               d_out(2)<=d_in(14);
               d_out(1)<=d_in(13);
               d_out(0)<=d_in(12);
     when "101"=>d_out(3)<=d_in(11); 
               d_out(2)<=d_in(10);
               d_out(1)<=d_in(9);
               d_out(0)<=d_in(8);
     when "110"=>d_out(3)<=d_in(7); 
               d_out(2)<=d_in(6);
               d_out(1)<=d_in(5);
               d_out(0)<=d_in(4);
     when "111"=>d_out(3)<=d_in(3); 
               d_out(2)<=d_in(2);
               d_out(1)<=d_in(1);
               d_out(0)<=d_in(0);
     when others=>
               null;
     end case;
  end if;
end process;
end scan;

library ieee;--译码
use ieee.std_logic_1164.all;
entity led is
    port(
         d_in:in std_logic_vector(3 downto 0);
         a:out std_logic;
         b:out std_logic;
         c:out std_logic;
         d:out std_logic;
         e:out std_logic;
         f:out std_logic;
         g:out std_logic);
end led;
architecture led of led is
begin
process(d_in)
type data_out is array(0 to 6) of std_logic ;    
variable outp: data_out;
begin
  case d_in is
     when "0000"=>outp :="1111110";
     when "0001"=>outp :="0110000";
     when "0010"=>outp:="1101101";
     when "0011"=>outp:="1111001";
     when "0100"=>outp:="0110011";
     when "0101"=>outp:="1011011";
     when "0110"=>outp:="1011111";
     when "0111"=>outp:="1110000";
     when "1000"=>outp:="1111111";
     when "1001"=>outp:="1111011";
     when "1010"=>outp:="1110111";
     when "1011"=>outp:="0011111";
     when "1100"=>outp:="1001110";
     when "1101"=>outp:="0111101";
     when "1110"=>outp:="1001111";
     when "1111"=>outp:="1000111";
     when others=>null;
   end case;
     a<=outp(0);
     b<=outp(1);  
     c<=outp(2);
     d<=outp(3); 
     e<=outp(4);
     f<=outp(5);
     g<=outp(6);
end process;
end led;    
     
 
library ieee;
use ieee.std_logic_1164.all;
entity fraq is
   port(fsin:in std_logic;
        clk:in std_logic;
        clkled:in std_logic;
        resetled:in std_logic;
        selled:out std_logic_vector(2 downto 0);
         led_a:out std_logic;
         led_b:out std_logic;
         led_c:out std_logic;
         led_d:out std_logic;
         led_e:out std_logic;
         led_f:out std_logic;
         led_g:out std_logic
        --dout:out std_logic_vector(31 downto 0)
);
end entity fraq;
architecture beva of fraq is

component oscdiv is
  port(cp:in std_logic;
        result: out std_logic
        );
end component oscdiv;  

component cnt10 is
   port(clk: in std_logic;--时钟信号
       clr: in std_logic;--清零信号
       ena: in std_logic;--使能信号
       --cq:out integer range 0 to 15;
        cq: out std_logic_vector(3 downto 0);
       --cq: in std_logic_vector(3 downto 0);--计数输出
       carry_out: out std_logic);--进位
end component cnt10;
component reg32b is
   port(load: in std_logic;
        din: in std_logic_vector(31 downto 0);
        dout: out std_logic_vector(31 downto 0));
end component reg32b;
component testctl is
   port(clk:in std_logic;
      tsten: out std_logic;
      clr_cnt: out std_logic;
      load: out std_logic);
end component testctl;
component dispscan is
    port(d_in:in std_logic_vector(31 downto 0);
         reset: in std_logic;--显示重设
         clkdsp:in std_logic;--数码管显示时钟信号
         sel:out std_logic_vector(2 downto 0);--数码管选择
         d_out:out std_logic_vector(3 downto 0));
end component dispscan;
component led is
     port(d_in:in std_logic_vector(3 downto 0);
         a:out std_logic;
         b:out std_logic;
         c:out std_logic;
         d:out std_logic;
         e:out std_logic;
         f:out std_logic;
         g:out std_logic);
end component led; 
signal se,sc,sl:std_logic;
signal s1,s2,s3,s4,s5,s6,s7,s8:std_logic;
signal sd:std_logic_vector(31 downto 0);
signal dout:std_logic_vector(31 downto 0);
signal din_out:std_logic_vector(3 downto 0);
signal clk1:std_logic;
begin
 u0:oscdiv port map(cp=>clk,result=>clk1);
 u1:testctl port map(clk=>clk1,tsten=>se,clr_cnt=>sc,load=>sl);
 u2:cnt10 port map(clk=>fsin,clr=>sc,ena=>se,cq=>sd(3 downto 0),carry_out=>s1);
 u3:cnt10 port map(clk=>s1,clr=>sc,ena=>se,cq=>sd(7 downto 4),carry_out=>s2);
 u4:cnt10 port map(s2,sc,se,sd(11 downto 8),s3);
 u5:cnt10 port map(s3,sc,se,sd(15 downto 12),s4);
 u6:cnt10 port map(s4,sc,se,sd(19 downto 16),s5);
 u7:cnt10 port map(s5,sc,se,sd(23 downto 20),s6);
 u8:cnt10 port map(s6,sc,se,sd(27 downto 24),s7);
 u9:cnt10 port map(s7,sc,se,sd(31 downto 28),s8);
 u10:reg32b port map(load=>sl,din=>sd(31 downto 0),dout=>dout);
 u11:dispscan port map(d_in=>dout,reset=>resetled,
                      clkdsp=>clkled,sel=>selled,d_out=>din_out);
 u12:led port map(d_in=>din_out,a=>led_a,
                                b=>led_b,
                                c=>led_c,
                                d=>led_d,
                                e=>led_e,
                                f=>led_f,
                                g=>led_g);
end architecture beva;