cnt10.vhd

来自「基于VHDL语言的频率计具有高速计频」· VHDL 代码 · 共 39 行

library ieee;--十进制计数器
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt10 is
  port(clk: in std_logic;--时钟信号
       clr: in std_logic;--清零信号
       ena: in std_logic;--使能信号
       --cq:out integer range 0 to 15;
        cq: out std_logic_vector(3 downto 0);
       --cq: in std_logic_vector(3 downto 0);--计数输出
       carry_out: out std_logic);--进位
end entity cnt10;
architecture art of cnt10 is
--signal cqi:integer range 0 to 15;
signal cqi: std_logic_vector(3 downto 0);
begin
process(clk,clr,ena)
begin
if clr='1' then cqi<="0000";
 elsif clk'event and clk='1' then
  if  ena='1' then 
   --cqi<=cqi+1;
   if cqi<9 then cqi<=cqi+1;
   else cqi<="0000";
   --if cqi="1001" then cqi="0000";
   --else cqi=cqi+1;
   end if;
 end if;
--end if; 
end if;
end process;
process(cqi) is
begin
if cqi=9 then carry_out<='1';
else carry_out<='0';
end if;
end process;
cq<=cqi;
end architecture art;