add_fcw.vhd

来自「采用DDS技术的波形发生器」· VHDL 代码 · 共 29 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--频率字累加器
entity add_fcw is
port(clr:in std_logic;--清零复位,0为复位
     clk:in std_logic;--
     fcw:in std_logic_vector(7 downto 0);
     sum:out std_logic_vector(9 downto 0));
end add_fcw;

architecture add of add_fcw is
signal tmp:std_logic_vector(9 downto 0);
signal fcwtmp:std_logic_vector(7 downto 0);
begin
    process(clk,clr)
     begin
     if clr='0' then 
        sum<=(others=>'0');
        tmp<=(others=>'0');
     else
        if rising_edge(clk) then
          tmp<=tmp+fcw+1;
          sum<=tmp;
         end if;     
     end if;
     end process;
end ;