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VHDL/FPGA/Verilog 空调系统有限状态自动机编码
空调系统有限状态自动机编码，各个源描述的编译顺序conditioner.vhd，conditioner_stim.vhd
VHDL/FPGA/Verilog Stereo-Vision circuit description, Aug 2002, Ahmad Darabiha This design contains four top level ci
Stereo-Vision circuit description, Aug 2002,
Ahmad Darabiha
This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and
sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical and the
sub-circuits can be used as smaller benchmarks.
VHDL/FPGA/Verilog 该文件是一份本人设计的实验报告
该文件是一份本人设计的实验报告，报告内详细说明了用VHDL语言，设计一个三位动态显示的计数器。采用模块化得设计，设计通过了仿真以及下载实现。总的文件是：shixian.vhd,下面包括四个元件：jishu1000.vhd,xzqh.vhd,senvedec.vhd,disp.vhd. ...
其他 The Hardware folder contains the following files:- 1) Sram_Interface.bit -----------------> Bi
The Hardware folder contains the following files:-
1) Sram_Interface.bit -----------------> Bitstream File
2) Sram_Interface.ucf -----------------> UCF File
3) Sram_Interface.vhd -----------------> Main Entity
4) Sram_Interface_tb.vhd ------------> Test Bench
5) SRAM_RD_WR.vhd ------------> S ...
技术资料 MP3解码的VHDL实现
·MP3解码的VHDL实现文件列表: mp3_decoder ...........\Filterbank ...........\..........\all_types.vhd ...........\..........\filterbank.vhd ...........\..........\filterbank_pac
教程资料 UART 4 UART参考设计，Xilinx提供VHDL代码
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl
This zip file contains the following folders:
 \vhdl_source  -- Source VHDL files:
     uart.vhd  - top level file
     txmit.vhd - transmit portion of uart
 &nb ...
可编程逻辑 UART 4 UART参考设计，Xilinx提供VHDL代码
UART 4 UART参考设计，Xilinx提供VHDL代码 uart_vhdl
This zip file contains the following folders:
 \vhdl_source  -- Source VHDL files:
     uart.vhd  - top level file
     txmit.vhd - transmit portion of uart
 &nb ...
VHDL/FPGA/Verilog Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested i
Working RS232 controller running at 9600 Hz.
Consist of Transmitter and Receiver Module.
Tested in FPGA Spartan 3
Included files for testing at FPGA
- Scan4digit .vhd - to display at 7 sgement display
- D4to7 .vhd - Convert HEX decimal to ASCII code.
技术资料 电子时钟VHDL顶层程序
顶层设计VHDL程序
--文件名：clock.vhd。
--功能：时钟的顶层设计。
VHDL/FPGA/Verilog The Synthetic PIC Verion 1.1 This a VHDL synthesizable model of a simple PIC 16C5x microcontro
The Synthetic PIC
Verion 1.1
This a VHDL synthesizable model of a simple PIC 16C5x microcontroller.
It is not, and is not intended as, a high fidelity circuit simulation.
This package includes the following files. Note that the license agreement
is stated in the main VHDL file, PICCPU.VHD and com ...