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VHDL/FPGA/Verilog <Floating Point Unit Core> fpupack.vhd pre_norm_addsub.vhd addsub_28.vhd post_norm_addsub.
<Floating Point Unit Core>
fpupack.vhd
pre_norm_addsub.vhd
addsub_28.vhd
post_norm_addsub.vhd
pre_norm_mul.vhd
mul_24.vhd
vcom serial_mul.vhd
post_norm_mul.vhd
pre_norm_div.vhd
serial_div.vhd
post_norm_div.vhd
pre_norm_sqrt.vhd
sqrt.vhd
post_norm_sqrt.vhd
comppack.vhd
fpu.vhd
***For simulation **** ...
其他嵌入式/单片机内容 Assembler source code for a AT90S2313 microcontroller used in an interface for reading, programming
Assembler source code for a AT90S2313 microcontroller used in an interface for reading, programming and bulk erasing serial flash of the ST25P16 and SP25P32 family used on the WGT624v3 Netgears Router.
技术资料 BR9020数据手册
1, 2, and 4k bit EEPROMs for direct
connection to serial ports BR9010 /BR9010F /BR9010FV /BR9020/BR9020F / BR9040 / BR9040F
技术资料 UART
自己用VB写的串口调试程序，对于单片机之类的调试非常好用，自己感觉比网上能下到的那些好用-Its own serial port using VB to write a debugger for de
技术资料 test_commapi
API的串口通讯程序，可设置为数据发送或者字符发送，可设置自动发送；接收可以为数据也可以为字符方式，有实时的错误报告。-API serial communication procedures
单片机编程 3-V TO 5.5-V MULTICHANNEL RS-2
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-23 ...
文章/文档 The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general co
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control
and data transfer communication between ICs.
Some of the features of the I2C bus are:
&#8226 Two signal lines, a serial data line (SDA) and a serial clock line (SCL), and ground are required. A
...
测试测量 XAPP713 -Virtex-4 RocketIO误码率测试器
&nbsp;
The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in t ...
VHDL/FPGA/Verilog -- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right
-- DESCRIPTION : Shift register
-- Type : univ
-- Width : 4
-- Shift direction: right/left (right active high)
--
-- CLK active : high
-- CLR active : high
-- CLR type : synchronous
-- SET active : high
-- SET type : synchronous
-- LOAD active : high
-- CE active : high
-- SERIAL input : SI ...
技术资料 DSP集成电路设计
Digital signal processor is a new type of structure and high—performance microprocessors，
especially suitable for signal processing，communications，voice processing，image／graphics，
military,instrumentation，automation，medical and household．DSP has achieved significant
progress as its powerfu ...