📦 DSP集成电路设计 - 免费下载

Digital signal processor is a new type of structure and high—performance microprocessors， especially suitable for signal processing，communications，voice processing，image／graphics， military,instrumentation，automation，medical and household．DSP has achieved significant progress as its powerful processing capabilities and high flexibility meet the signal processing tasks on real—time，high—speed and accuracy requirements． In this paper,reliable and high—speed synchronous serial interface have been researched and designed in the outside of 32-bit DSP．SPI(Serial Peripheral Interface)bus is an intercommunication，synchronous and serial communication interface bus，which is widely applied to the EEPROM，the external set FLASHRAM，network controller,LCD display driver,A／D converter,MCU，real-time clock and the digital signal decoder and SO on．In this paper,according to industry standard SPI bus，this work is the design of a highly reliable and high-speed SPI bus，and design some important parts of the SPl with hardware description language，such as synchronization logic clock，asynchronous logic clock，data transceiver and signal detector．During the design process，the actual a mass of data increase the burden of CPU．So this paper increase two 1 6-word deep FIFO buffer in the SPI，which greatly improve the speed of receiving and sending data，reduce the CPU open sales，decrease interruption frequency of receiving and sending，enhance the efficiency of serial transmission．A Time Delay Transfer function was increased，the speed of sending data is controllable adjustable． Optimized data transfer mode，thus the reliability of data is further improved that can have practical significance and application． The entire circuit is designed to be completed by flexible Verilog HDL language，and verified by Cadence’S NC·Verilog&Verilog—XL software．Not only simulate the internal SPI modules，but also realize the SPI overall system simulation．Finally,according to the principles of layout design of integrated circuits，high—speed serial peripheral interface circuit layout iS implemented． Keywords：DSP；interface；FIFO；FSM；divider

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