搜索：Logic - 虫虫下载站

技术资料  TMS320C54X数字处理芯片与外设之间高速数据传输的实现

·摘要：  实时性是DSP处理系统常见的要求,本文论述了采用CPLD(ComplexProgrammable Logic Device)以流水栈方式提高DSP系统端口数据传输速度的优越性和基本实现方法,并给出了部分代码和设置参数.  

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320C

VHDL/FPGA/Verilog vhdl编写

vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous clocked inputs (latched on each clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output ...

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vhdl 编写

电源技术  高效率,高密度,高电流应用的多相转换器

&nbsp; As logic systems get larger and more complex, theirsupply current requirements continue to rise. Systemsrequiring 100A are fairly common. A high current powersupply to meet such requirements usually requires parallelingseveral power regulators to alleviate the thermalstress on the individ ...

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高效率密度多相转换器高电流

嵌入式/单片机编程  cheetek方案的数码相框已经开始占据了相当大市场份额

cheetek方案的数码相框已经开始占据了相当大市场份额，了解其内部结构成为一种必要，这是它的原理图，对从事DPF开发的人员有很高的参考价值！请用pads logic 软件及其他相关打开浏览

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cheetek 方案数码相框

源码  源代码LIBRARY IEEE USE IEEE

通用寄存器的部分代码 LIBRARY IEEE USE IEEE.STD_LOGIC_1164.ALL ENTITY traffic IS PORT(clk,sm,sb:IN bit mr,my,mg,br,by,bg:OUT bit ) END traffic

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IEEE LIBRARY USE 源代码

技术资料  基于Petri 网的工作流逻辑化简规则的矩阵表示

Petri 网是一种很有效的模型描述语言，尤其适合描述工作流。[1]给出了基于Petri 网的工作流逻辑（WF_logic）化简规则，这里则借助矩阵及矩阵运算或矩阵上的初等变换来实现这些化简规

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Petri

allegro Verilog编码中的非阻塞性赋值

&nbsp; One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...

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Verilog 编码非阻塞性赋值

Mentor Design Safe Verilog State Machine（Synplicity）

&nbsp; One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability ana ...

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Synplicity Machine Verilog Design

可编程逻辑  Verilog编码中的非阻塞性赋值

&nbsp; One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assi ...

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Verilog 编码非阻塞性赋值

可编程逻辑  Design Safe Verilog State Machine（Synplicity）