虫虫首页|资源下载|资源专辑|精品软件
登录|注册

您现在的位置是:虫虫下载站 > 资源下载 > 可编程逻辑 > Design Safe Verilog State Machine(Synplicity)

Design Safe Verilog State Machine(Synplicity)

  • 资源大小:134 K
  • 上传时间: 2013-10-20
  • 上传用户:ekhlr
  • 资源积分:2 下载积分
  • 标      签: Synplicity Machine Verilog Design

资 源 简 介

 

One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

相 关 资 源