uart_txd.vht

基于verilog hdl的UART串口发送子程序。

t_prcs_clk_out: PROCESS
BEGIN
	clk_out_expected <= 'X';
WAIT;
END PROCESS t_prcs_clk_out;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(TI_expected,TXD_expected,clk_out_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(TI,TXD,clk_out)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_TI_exp : STD_LOGIC := 'U';
VARIABLE last_TXD_exp : STD_LOGIC := 'U';
VARIABLE last_clk_out_exp : STD_LOGIC := 'U';

VARIABLE on_first_change : trackvec := "111";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,TI_name);write(txt,string'(" = "));write(txt,TI_expected_prev);
	write(txt,string'("| expected "));write(txt,TXD_name);write(txt,string'(" = "));write(txt,TXD_expected_prev);
	write(txt,string'("| expected "));write(txt,clk_out_name);write(txt,string'(" = "));write(txt,clk_out_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,TI_name);write(txt,string'(" = "));write(txt,TI_prev);
	write(txt,string'("| real "));write(txt,TXD_name);write(txt,string'(" = "));write(txt,TXD_prev);
	write(txt,string'("| real "));write(txt,clk_out_name);write(txt,string'(" = "));write(txt,clk_out_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( TI_expected_prev /= 'X' ) AND (TI_expected_prev /= 'U' ) AND (TI_prev /= TI_expected_prev) AND (
	(TI_expected_prev /= last_TI_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("TI",TI_expected_prev,TI_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_TI_exp := TI_expected_prev;
END IF;
IF ( TXD_expected_prev /= 'X' ) AND (TXD_expected_prev /= 'U' ) AND (TXD_prev /= TXD_expected_prev) AND (
	(TXD_expected_prev /= last_TXD_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("TXD",TXD_expected_prev,TXD_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_TXD_exp := TXD_expected_prev;
END IF;
IF ( clk_out_expected_prev /= 'X' ) AND (clk_out_expected_prev /= 'U' ) AND (clk_out_prev /= clk_out_expected_prev) AND (
	(clk_out_expected_prev /= last_clk_out_exp) OR
	(on_first_change(3) = '1')
		) THEN
	throw_error("clk_out",clk_out_expected_prev,clk_out_prev);
	num_mismatches(2) <= num_mismatches(2) + 1;
	on_first_change(3) := '0';
	last_clk_out_exp := clk_out_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 1000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1) + num_mismatches(2);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.uart_txd_vhd_tb_types.ALL;                                         

ENTITY uart_txd_vhd_vec_tst IS
END uart_txd_vhd_vec_tst;
ARCHITECTURE uart_txd_arch OF uart_txd_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL TI : STD_LOGIC;
SIGNAL TXD : STD_LOGIC;
SIGNAL clk_in : STD_LOGIC;
SIGNAL clk_out : STD_LOGIC;
SIGNAL data_in : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL txd_en : STD_LOGIC;
SIGNAL sampler : sample_type;

COMPONENT uart_txd
	PORT (
	TI : OUT STD_LOGIC;
	TXD : OUT STD_LOGIC;
	clk_in : IN STD_LOGIC;
	clk_out : OUT STD_LOGIC;
	data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	txd_en : IN STD_LOGIC
	);
END COMPONENT;
COMPONENT uart_txd_vhd_check_tst
PORT ( 
	TI : IN STD_LOGIC;
	TXD : IN STD_LOGIC;
	clk_out : IN STD_LOGIC;
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT uart_txd_vhd_sample_tst
PORT (
	clk_in : IN STD_LOGIC;
	data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	txd_en : IN STD_LOGIC;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : uart_txd
	PORT MAP (
-- list connections between master ports and signals
	TI => TI,
	TXD => TXD,
	clk_in => clk_in,
	clk_out => clk_out,
	data_in => data_in,
	txd_en => txd_en
	);

-- txd_en
t_prcs_txd_en: PROCESS
BEGIN
	txd_en <= '0';
WAIT;
END PROCESS t_prcs_txd_en;

-- clk_in
t_prcs_clk_in: PROCESS
BEGIN
	clk_in <= '0';
WAIT;
END PROCESS t_prcs_clk_in;
-- data_in[7]
t_prcs_data_in_7: PROCESS
BEGIN
	data_in(7) <= '0';
WAIT;
END PROCESS t_prcs_data_in_7;
-- data_in[6]
t_prcs_data_in_6: PROCESS
BEGIN
	data_in(6) <= '0';
WAIT;
END PROCESS t_prcs_data_in_6;
-- data_in[5]
t_prcs_data_in_5: PROCESS
BEGIN
	data_in(5) <= '0';
WAIT;
END PROCESS t_prcs_data_in_5;
-- data_in[4]
t_prcs_data_in_4: PROCESS
BEGIN
	data_in(4) <= '0';
WAIT;
END PROCESS t_prcs_data_in_4;
-- data_in[3]
t_prcs_data_in_3: PROCESS
BEGIN
	data_in(3) <= '0';
WAIT;
END PROCESS t_prcs_data_in_3;
-- data_in[2]
t_prcs_data_in_2: PROCESS
BEGIN
	data_in(2) <= '0';
WAIT;
END PROCESS t_prcs_data_in_2;
-- data_in[1]
t_prcs_data_in_1: PROCESS
BEGIN
	data_in(1) <= '0';
WAIT;
END PROCESS t_prcs_data_in_1;
-- data_in[0]
t_prcs_data_in_0: PROCESS
BEGIN
	data_in(0) <= '0';
WAIT;
END PROCESS t_prcs_data_in_0;
tb_sample : uart_txd_vhd_sample_tst
PORT MAP (
	clk_in => clk_in,
	data_in => data_in,
	txd_en => txd_en,
	sampler => sampler
	);

tb_out : uart_txd_vhd_check_tst
PORT MAP (
	TI => TI,
	TXD => TXD,
	clk_out => clk_out,
	sampler => sampler
	);
END uart_txd_arch;