prev_cmp_uart_txd.qmsg

基于verilog hdl的UART串口发送子程序。

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "3 " "Warning: Found 3 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "clk_out 0 " "Info: Pin \"clk_out\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TXD 0 " "Info: Pin \"TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TI 0 " "Info: Pin \"TI\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 -1}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "3 " "Warning: Following 3 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "clk_out GND " "Info: Pin clk_out has GND driving its datain port" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { clk_out } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 20 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk_out } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TXD GND " "Info: Pin TXD has GND driving its datain port" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { TXD } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 21 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { TXD } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "TI GND " "Info: Pin TI has GND driving its datain port" {  } { { "d:/altera/90/quartus/bin/pin_planner.ppl" "" { PinPlanner "d:/altera/90/quartus/bin/pin_planner.ppl" { TI } } } { "uart_txd.v" "" { Text "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.v" 22 -1 0 } } { "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/90/quartus/bin/TimingClosureFloorplan.fld" "" "" { TI } "NODE_NAME" } }  } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1}  } {  } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.fit.smsg " "Info: Generated suppressed messages file F:/My   Project/Verilog HDL/UART/uart_txd/uart_txd.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "197 " "Info: Peak virtual memory: 197 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 14:35:01 2009 " "Info: Processing ended: Mon May 11 14:35:01 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 11 14:35:06 2009 " "Info: Processing started: Mon May 11 14:35:06 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Info: Writing out detailed assembly data for power analysis" {  } {  } 0 0 "Writing out detailed assembly data for power analysis" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Peak virtual memory: 156 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 14:35:13 2009 " "Info: Processing ended: Mon May 11 14:35:13 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:07 " "Info: Elapsed time: 00:00:07" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Info: Total CPU time (on all processors): 00:00:05" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Mon May 11 14:35:16 2009 " "Info: Processing started: Mon May 11 14:35:16 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd --timing_analysis_only" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IQCU_PARALLEL_AUTODETECT_ONE_PROCESSOR" "" "Info: Only one processor detected - disabling parallel compilation" {  } {  } 0 0 "Only one processor detected - disabling parallel compilation" 0 0 "" 0 -1}
{ "Warning" "WTAN_NOTHING_TO_TIMING_ANALYZE" "" "Warning: No paths found for timing analysis" {  } {  } 0 0 "No paths found for timing analysis" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Peak virtual memory: 134 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Mon May 11 14:35:18 2009 " "Info: Processing ended: Mon May 11 14:35:18 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 22 s " "Info: Quartus II Full Compilation was successful. 0 errors, 22 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}