uart_txd.hier_info

来自「基于verilog hdl的UART串口发送子程序。」· HIER_INFO 代码 · 共 18 行

|uart_txd
clk_in => txd_reg.CLK
clk_in => TI~reg0.CLK
clk_out <= <GND>
data_in[0] => ~NO_FANOUT~
data_in[1] => ~NO_FANOUT~
data_in[2] => ~NO_FANOUT~
data_in[3] => ~NO_FANOUT~
data_in[4] => ~NO_FANOUT~
data_in[5] => ~NO_FANOUT~
data_in[6] => ~NO_FANOUT~
data_in[7] => ~NO_FANOUT~
TXD <= txd_reg.DB_MAX_OUTPUT_PORT_TYPE
TI <= TI~reg0.DB_MAX_OUTPUT_PORT_TYPE
txd_en => ~NO_FANOUT~