uart_txd.fit.rpt

基于verilog hdl的UART串口发送子程序。

; Base pin-out file on sameframe device        ; Off                      ;
+----------------------------------------------+--------------------------+


+------------------------------------+
; Operating Settings and Conditions  ;
+---------------------------+--------+
; Setting                   ; Value  ;
+---------------------------+--------+
; Nominal Core Voltage      ; 1.20 V ;
; Low Junction Temperature  ; 0 癈   ;
; High Junction Temperature ; 85 癈  ;
+---------------------------+--------+


+----------------------------+
; Advanced Data - General    ;
+--------------------+-------+
; Name               ; Value ;
+--------------------+-------+
; Status Code        ; 0     ;
; Desired User Slack ; 0     ;
; Fit Attempts       ; 1     ;
+--------------------+-------+


+-------------------------------------------------------------------------------+
; Advanced Data - Placement Preparation                                         ;
+------------------------------------------------------------------+------------+
; Name                                                             ; Value      ;
+------------------------------------------------------------------+------------+
; Auto Fit Point 1 - Fit Attempt 1                                 ; ff         ;
; Mid Wire Use - Fit Attempt 1                                     ; 0          ;
; Mid Slack - Fit Attempt 1                                        ; 2147483639 ;
; Internal Atom Count - Fit Attempt 1                              ; 1          ;
; LE/ALM Count - Fit Attempt 1                                     ; 1          ;
; LAB Count - Fit Attempt 1                                        ; 1          ;
; Outputs per Lab - Fit Attempt 1                                  ; 0.000      ;
; Inputs per LAB - Fit Attempt 1                                   ; 0.000      ;
; Global Inputs per LAB - Fit Attempt 1                            ; 0.000      ;
; LAB Constraint 'non-global clock + sync load' - Fit Attempt 1    ; 0:1        ;
; LAB Constraint 'non-global controls' - Fit Attempt 1             ; 0:1        ;
; LAB Constraint 'non-global + aclr' - Fit Attempt 1               ; 0:1        ;
; LAB Constraint 'global non-clock non-aclr' - Fit Attempt 1       ; 0:1        ;
; LAB Constraint 'global controls' - Fit Attempt 1                 ; 0:1        ;
; LAB Constraint 'deterministic LABSMUXA/LABXMUXB' - Fit Attempt 1 ; 0:1        ;
; LAB Constraint 'deterministic LABSMUXC/LABXMUXD' - Fit Attempt 1 ; 0:1        ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1      ; 0:1        ;
; LAB Constraint 'aclr constraint' - Fit Attempt 1                 ; 0:1        ;
; LAB Constraint 'true sload_sclear pair' - Fit Attempt 1          ; 0:1        ;
; LAB Constraint 'constant sload_sclear pair' - Fit Attempt 1      ; 0:1        ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1        ; 0:1        ;
; LAB Constraint 'group hierarchy constraint' - Fit Attempt 1      ; 0:1        ;
; LEs in Chains - Fit Attempt 1                                    ; 0          ;
; LEs in Long Chains - Fit Attempt 1                               ; 0          ;
; LABs with Chains - Fit Attempt 1                                 ; 0          ;
; LABs with Multiple Chains - Fit Attempt 1                        ; 0          ;
; Time - Fit Attempt 1                                             ; 0          ;
; Time in tsm_tan.dll - Fit Attempt 1                              ; 0.016      ;
+------------------------------------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Placement                       ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Mid Wire Use - Fit Attempt 1       ; 0          ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 5 - Fit Attempt 1   ; ff         ;
; Mid Wire Use - Fit Attempt 1       ; 0          ;
; Mid Slack - Fit Attempt 1          ; 2147483639 ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Auto Fit Point 6 - Fit Attempt 1   ; ff         ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Late Slack - Fit Attempt 1         ; 2147483639 ;
; Peak Regional Wire - Fit Attempt 1 ; 0.000      ;
; Auto Fit Point 7 - Fit Attempt 1   ; ff         ;
; Time - Fit Attempt 1               ; 0          ;
+------------------------------------+------------+


+-------------------------------------------------+
; Advanced Data - Routing                         ;
+------------------------------------+------------+
; Name                               ; Value      ;
+------------------------------------+------------+
; Early Wire Use - Fit Attempt 1     ; 0          ;
; Peak Regional Wire - Fit Attempt 1 ; 0          ;
; Early Slack - Fit Attempt 1        ; 2147483639 ;
; Late Wire Use - Fit Attempt 1      ; 0          ;
; Time - Fit Attempt 1               ; 0          ;
+------------------------------------+------------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
    Info: Processing started: Mon May 11 14:39:20 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off uart_txd -c uart_txd
Info: Only one processor detected - disabling parallel compilation
Info: Selected device EP2C5T144C8 for design "uart_txd"
Info: Low junction temperature is 0 degrees C
Info: High junction temperature is 85 degrees C
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EP2C5T144I8 is compatible
    Info: Device EP2C8T144C8 is compatible
    Info: Device EP2C8T144I8 is compatible
Info: Fitter converted 3 user pins into dedicated programming pins
    Info: Pin ~ASDO~ is reserved at location 1
    Info: Pin ~nCSO~ is reserved at location 2
    Info: Pin ~LVDS41p/nCEO~ is reserved at location 76
Warning: No exact pin location assignment(s) for 13 pins of 13 total pins
    Info: Pin clk_in not assigned to an exact location on the device
    Info: Pin clk_out not assigned to an exact location on the device
    Info: Pin data_in[0] not assigned to an exact location on the device
    Info: Pin data_in[1] not assigned to an exact location on the device
    Info: Pin data_in[2] not assigned to an exact location on the device