_info

基于verilog hdl的UART串口发送子程序。

m255
K3
13
cModel Technology
dD:\altera\90\modelsim_ae\examples
vuart_txd_vlg_check_tst
!s100 3ATRSS66kEWXQABZ_@?fM3
I>^<:NA@Kd^60bYZE;K8<M3
VT2dS05Y0?7:;?9E3^jP0<2
Z0 dF:\My   Project\Verilog HDL\UART\uart_txd
Z1 w1242023592
Z2 8F:/My   Project/Verilog HDL/UART/uart_txd/export/uart_txd.v
Z3 FF:/My   Project/Verilog HDL/UART/uart_txd/export/uart_txd.v
L0 61
Z4 OV;L;6.4a;39
r1
!s85 0
31
Z5 o-work work -nocovercells -O0
vuart_txd_vlg_sample_tst
!s100 1[=jXRW5XP>9Mh25ZO6i=3
I^aB[aE8zYc5l<OMO9W8P]2
VmnbDU[4JBfa2[8@k;LY1]3
Z6 dF:\My   Project\Verilog HDL\UART\uart_txd
R1
R2
R3
L0 29
R4
r1
!s85 0
31
R5
vuart_txd_vlg_vec_tst
!s100 :RM88LT3;EC73k3S4Ing53
I2LeKi;7SJiMIOFjQLTA5G1
V42T<7Plk]Jjc0@[Dz9ABg3
R6
R1
R2
R3
L0 207
R4
r1
!s85 0
31
R5