uart_txd.root_partition.map.kpt

基于verilog hdl的UART串口发送子程序。

<kpt_db name="uart_txd.map_bb" kpt_version="1.1">
  <key_points_set type="reference" hier_sep="/">
    <key_point id="1" type="register">
      <name>txd_reg</name>
      <attributes_list>
        <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
      </attributes_list>
    </key_point>
    <key_point id="2" type="register">
      <name>TI~reg0</name>
      <attributes_list>
        <attribute name="_KPT_INT_ELIM_STAT_">SA0</attribute>
      </attributes_list>
    </key_point>
  </key_points_set>
  <key_points_set type="transition" hier_sep="|">
  </key_points_set>
  <key_points_set type="transformed" hier_sep="|">
  </key_points_set>
  <transformations_set hier_sep="|">
  </transformations_set>
</kpt_db>