basic_base2_mul_seq.v

上传文件为：常用乘法器verilog设计.rar

// N比特乘M比特的二进制时序乘法器
module basic_base2_mul_seq(x_in, y_in, clk, ini, p_out, done);
	parameter 	N = 8,
				M = 4;
	
	input	clk, ini;
	input  [N-1:0] x_in;
	input  [M-1:0] y_in;
	output 	done;
	reg 	done;
	output	[N+M-1:0] p_out;
	reg		[N+M-1:0] p_out;

	integer counter;
	reg [M:0] temp_p;
	reg [N-1:0] x_reg;
	reg [M-1:0] y_reg, p_reg;
	reg [N+M-1:0] p_out;
	always @(posedge clk)begin
		if(ini)begin
			x_reg <= x_in;
			y_reg <= y_in;
			p_reg <= 0;
			counter <= 0;
			done <= 0;
		end
		else if(counter < N)begin
			if(x_reg[0])
				temp_p = p_reg + y_reg;
			else
				temp_p = p_reg;
			p_reg <= temp_p[M:1];
			x_reg <= {temp_p[0], x_reg[N-1:1]};
			counter <= counter + 1;
		end
		else if(counter == N)begin
			p_out = {p_reg[M-1:0], x_reg[N-1:0]};
			done <= 1;
		end
	end
	
endmodule