led_clk_gen.vhd

可以显示六个BCD码的动态扫描七段数码管显示电路。有缓存

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY led_clk_gen IS
PORT(
      clk     :IN STD_LOGIC;
      clk_scan:BUFFER STD_LOGIC;
      CLK_FLICKER:OUT STD_LOGIC
);
END led_clk_gen;
ARCHITECTURE rtl OF led_clk_gen IS
SIGNAL cnt1 :INTEGER RANGE 0 TO 39999;
SIGNAL cnt2 :INTEGER RANGE 0 TO 149;
BEGIN
PROCESS(clk)
BEGIN
IF(clk'event and clk='1')THEN
IF(cnt1=cnt1'high)THEN
 cnt1<=0;
ELSE
cnt1<=cnt1+1;
END IF;
END IF;
END PROCESS;
PROCESS(clk_scan)
BEGIN
    IF(clk_scan'event and clk_scan='1')THEN
IF(cnt2=cnt2'high)THEN
 cnt2<=0;
ELSE
cnt2<=cnt2+1;
END IF;
END IF;
END PROCESS;
PROCESS(cnt1,clk)
BEGIN
   IF(clk'event and clk='1')THEN
IF cnt1>=cnt1'high/2+1 THEN
   clk_scan<='1';
ELSE
   clk_scan<='0';
END IF;
END IF;
END PROCESS;
PROCESS(cnt2,clk_scan)
BEGIN
   IF(clk_scan'event and clk_scan='1')THEN
IF cnt2>=cnt2'high/2+1 THEN
   clk_flicker<='1';
ELSE
   clk_flicker<='0';
END IF;
END IF;
END PROCESS;
END rtl;