disp_buf.vhd

来自「可以显示六个BCD码的动态扫描七段数码管显示电路。有缓存」· VHDL 代码 · 共 33 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY disp_buf IS
PORT(
    clk   :IN STD_LOGIC;
    ld    :IN STD_LOGIC;
    data  :IN STD_LOGIC_VECTOR(29 DOWNTO 0);
    addr  :IN STD_LOGIC_VECTOR(2 DOWNTO 0);
    sdata :IN STD_LOGIC_VECTOR(4 DOWNTO 0);
    wr    :IN STD_LOGIC;
    dataout:OUT STD_LOGIC_VECTOR(29 DOWNTO 0));
END disp_buf;
ARCHITECTURE rtl OF disp_buf IS
BEGIN
  PROCESS(clk)
BEGIN
  IF(clk'event AND clk='1')THEN
IF(ld='1')THEN
   dataout<=data;
ELSIF(wr='1')THEN
CASE addr IS
   WHEN"000"=>dataout(4 DOWNTO 0)<=sdata;
   WHEN"001"=>dataout(9 DOWNTO 5)<=sdata;
   WHEN"010"=>dataout(14 DOWNTO 10)<=sdata;
   WHEN"011"=>dataout(19 DOWNTO 15)<=sdata;
   WHEN"100"=>dataout(24 DOWNTO 20)<=sdata;
   WHEN"101"=>dataout(29 DOWNTO 25)<=sdata;
   WHEN OTHERS=>dataout(4 DOWNTO 0)<=sdata;
END CASE;
END IF;
END IF;
END PROCESS;
end rtl;