rciii.map.qmsg

niosII基础上实现的嵌入式网络驱动

{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_7_is_x cpu_0_test_bench.v(240) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(240): object \"av_ld_data_aligned_unfiltered_7_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0_test_bench.v" 240 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_8_is_x cpu_0_test_bench.v(241) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(241): object \"av_ld_data_aligned_unfiltered_8_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0_test_bench.v" 241 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "av_ld_data_aligned_unfiltered_9_is_x cpu_0_test_bench.v(242) " "Info: (10035) Verilog HDL or VHDL information at cpu_0_test_bench.v(242): object \"av_ld_data_aligned_unfiltered_9_is_x\" declared but not used" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0_test_bench.v" 242 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 cpu_0_test_bench.v(249) " "Warning: Verilog HDL assignment warning at cpu_0_test_bench.v(249): truncated value with size 32 to match size of target (1)" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0_test_bench.v" 249 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "cpu_0_test_bench.v(250) " "Warning: (10037) Verilog HDL or VHDL warning at cpu_0_test_bench.v(250): condition expression evaluates to a constant" {  } { { "cpu_0_test_bench.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0_test_bench.v" 250 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_rf_module rcIII:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf " "Info: Elaborating entity \"cpu_0_rf_module\" for hierarchy \"rcIII:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\"" {  } { { "cpu_0.v" "cpu_0_rf" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0.v" 1136 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "../../../../../quartus50/libraries/megafunctions/altsyncram.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file ../../../../../quartus50/libraries/megafunctions/altsyncram.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram " "Info: Found entity 1: altsyncram" {  } { { "altsyncram.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 425 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram rcIII:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram " "Info: Elaborating entity \"altsyncram\" for hierarchy \"rcIII:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\"" {  } { { "cpu_0.v" "the_altsyncram" { Text "C:/altera/kits/nios2/components/rcIII/system/cpu_0.v" 66 -1 0 } }  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_vuo1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_vuo1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_vuo1 " "Info: Found entity 1: altsyncram_vuo1" {  } { { "db/altsyncram_vuo1.tdf" "" { Text "C:/altera/kits/nios2/components/rcIII/system/db/altsyncram_vuo1.tdf" 34 1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_vuo1 rcIII:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\|altsyncram_vuo1:auto_generated " "Info: Elaborating entity \"altsyncram_vuo1\" for hierarchy \"rcIII:inst\|cpu_0:the_cpu_0\|cpu_0_rf_module:cpu_0_rf\|altsyncram:the_altsyncram\|altsyncram_vuo1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "c:/altera/quartus50/libraries/megafunctions/altsyncram.tdf" 903 3 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_RAM_s1_arbitrator rcIII:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1 " "Info: Elaborating entity \"data_RAM_s1_arbitrator\" for hierarchy \"rcIII:inst\|data_RAM_s1_arbitrator:the_data_RAM_s1\"" {  } { { "rcIII.v" "the_data_RAM_s1" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3302 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(822) " "Warning: Verilog HDL assignment warning at rcIII.v(822): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 822 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(823) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(823): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 823 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(837) " "Warning: Verilog HDL assignment warning at rcIII.v(837): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 837 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(840) " "Warning: Verilog HDL assignment warning at rcIII.v(840): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 840 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 rcIII.v(858) " "Warning: Verilog HDL assignment warning at rcIII.v(858): truncated value with size 32 to match size of target (3)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 858 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(868) " "Warning: Verilog HDL assignment warning at rcIII.v(868): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 868 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(884) " "Warning: Verilog HDL assignment warning at rcIII.v(884): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 884 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(885) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(885): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 885 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(886) " "Warning: Verilog HDL assignment warning at rcIII.v(886): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 886 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 rcIII.v(902) " "Warning: Verilog HDL assignment warning at rcIII.v(902): truncated value with size 2 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 902 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(908) " "Warning: Verilog HDL assignment warning at rcIII.v(908): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 908 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(909) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(909): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 909 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(928) " "Warning: Verilog HDL assignment warning at rcIII.v(928): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 928 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(929) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(929): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 929 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(930) " "Warning: Verilog HDL assignment warning at rcIII.v(930): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 930 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "2 1 rcIII.v(942) " "Warning: Verilog HDL assignment warning at rcIII.v(942): truncated value with size 2 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 942 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(948) " "Warning: Verilog HDL assignment warning at rcIII.v(948): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 948 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(949) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(949): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 949 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(988) " "Warning: Verilog HDL assignment warning at rcIII.v(988): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 988 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(999) " "Warning: Verilog HDL assignment warning at rcIII.v(999): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 999 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(1005) " "Warning: Verilog HDL assignment warning at rcIII.v(1005): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1005 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "25 8 rcIII.v(1025) " "Warning: Verilog HDL assignment warning at rcIII.v(1025): truncated value with size 25 to match size of target (8)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1025 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1032) " "Warning: Verilog HDL assignment warning at rcIII.v(1032): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1032 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(1033) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(1033): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1033 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1039) " "Warning: Verilog HDL assignment warning at rcIII.v(1039): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1039 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(1048) " "Warning: Verilog HDL assignment warning at rcIII.v(1048): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1048 0 0 } }  } 0}