rciii.map.qmsg

niosII基础上实现的嵌入式网络驱动

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version " "Info: Version 5.0 Build 171 11/03/2005 Service Pack 2 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Feb 10 23:11:24 2007 " "Info: Processing started: Sat Feb 10 23:11:24 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off rcIII -c rcIII " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off rcIII -c rcIII" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "rcIII_top.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file rcIII_top.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 rcIII_top " "Info: Found entity 1: rcIII_top" {  } { { "rcIII_top.bdf" "" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { } } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "rcIII_top " "Info: Elaborating entity \"rcIII_top\" for the top level hierarchy" {  } {  } 0}
{ "Info" "ISGN_SEARCH_FILE" "rcIII.v 13 13 " "Info: Using design file rcIII.v, which is not specified as a design file for the current project, but contains definitions for 13 design units and 13 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 cpu_0_data_master_arbitrator " "Info: Found entity 1: cpu_0_data_master_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 21 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "2 cpu_0_instruction_master_arbitrator " "Info: Found entity 2: cpu_0_instruction_master_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 409 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "3 data_RAM_s1_arbitrator " "Info: Found entity 3: data_RAM_s1_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 697 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "4 firmware_ROM_s1_arbitrator " "Info: Found entity 4: firmware_ROM_s1_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1096 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "5 jtag_uart_0_avalon_jtag_slave_arbitrator " "Info: Found entity 5: jtag_uart_0_avalon_jtag_slave_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1495 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "6 payload_buffer_s1_arbitrator " "Info: Found entity 6: payload_buffer_s1_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 1746 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "7 sysid_control_slave_arbitrator " "Info: Found entity 7: sysid_control_slave_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2167 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "8 tri_state_bridge_0_avalon_slave_arbitrator " "Info: Found entity 8: tri_state_bridge_0_avalon_slave_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2354 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "9 tri_state_bridge_0_bridge_arbitrator " "Info: Found entity 9: tri_state_bridge_0_bridge_arbitrator" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2955 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "10 rcIII_reset_clk_domain_synch_module " "Info: Found entity 10: rcIII_reset_clk_domain_synch_module" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 2963 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "11 rcIII " "Info: Found entity 11: rcIII" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3003 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "12 ext_flash_lane0_module " "Info: Found entity 12: ext_flash_lane0_module" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3537 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "13 ext_flash " "Info: Found entity 13: ext_flash" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3623 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rcIII rcIII:inst " "Info: Elaborating entity \"rcIII\" for hierarchy \"rcIII:inst\"" {  } { { "rcIII_top.bdf" "inst" { Schematic "C:/altera/kits/nios2/components/rcIII/system/rcIII_top.bdf" { { 40 632 896 216 "inst" "" } } } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(3526) " "Warning: Verilog HDL assignment warning at rcIII.v(3526): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3526 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(3530) " "Warning: Verilog HDL assignment warning at rcIII.v(3530): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3530 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_data_master_arbitrator rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master " "Info: Elaborating entity \"cpu_0_data_master_arbitrator\" for hierarchy \"rcIII:inst\|cpu_0_data_master_arbitrator:the_cpu_0_data_master\"" {  } { { "rcIII.v" "the_cpu_0_data_master" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3214 -1 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(180) " "Warning: Verilog HDL assignment warning at rcIII.v(180): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 180 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(186) " "Warning: Verilog HDL assignment warning at rcIII.v(186): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 186 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "25 1 rcIII.v(192) " "Warning: Verilog HDL assignment warning at rcIII.v(192): truncated value with size 25 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 192 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(238) " "Warning: Verilog HDL assignment warning at rcIII.v(238): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 238 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(239) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(239): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 239 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(240) " "Warning: Verilog HDL assignment warning at rcIII.v(240): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 240 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(252) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(252): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 252 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(298) " "Warning: Verilog HDL assignment warning at rcIII.v(298): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 298 0 0 } }  } 0}
{ "Warning" "WVRFX_VRFC_CONDITION_EXP_IS_CONST" "rcIII.v(299) " "Warning: (10037) Verilog HDL or VHDL warning at rcIII.v(299): condition expression evaluates to a constant" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 299 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(309) " "Warning: Verilog HDL assignment warning at rcIII.v(309): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 309 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 rcIII.v(323) " "Warning: Verilog HDL assignment warning at rcIII.v(323): truncated value with size 32 to match size of target (16)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 323 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(334) " "Warning: Verilog HDL assignment warning at rcIII.v(334): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 334 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(352) " "Warning: Verilog HDL assignment warning at rcIII.v(352): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 352 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 rcIII.v(365) " "Warning: Verilog HDL assignment warning at rcIII.v(365): truncated value with size 32 to match size of target (8)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 365 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 rcIII.v(378) " "Warning: Verilog HDL assignment warning at rcIII.v(378): truncated value with size 32 to match size of target (8)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 378 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 rcIII.v(391) " "Warning: Verilog HDL assignment warning at rcIII.v(391): truncated value with size 32 to match size of target (8)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 391 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cpu_0_instruction_master_arbitrator rcIII:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master " "Info: Elaborating entity \"cpu_0_instruction_master_arbitrator\" for hierarchy \"rcIII:inst\|cpu_0_instruction_master_arbitrator:the_cpu_0_instruction_master\"" {  } { { "rcIII.v" "the_cpu_0_instruction_master" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 3252 -1 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "active_and_waiting_last_time rcIII.v(484) " "Info: (10035) Verilog HDL or VHDL information at rcIII.v(484): object \"active_and_waiting_last_time\" declared but not used" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 484 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_address_last_time rcIII.v(485) " "Info: (10035) Verilog HDL or VHDL information at rcIII.v(485): object \"cpu_0_instruction_master_address_last_time\" declared but not used" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 485 0 0 } }  } 0}
{ "Info" "IVRFX_VRFC_OBJECT_DECLARED_NOT_USED" "cpu_0_instruction_master_read_last_time rcIII.v(489) " "Info: (10035) Verilog HDL or VHDL information at rcIII.v(489): object \"cpu_0_instruction_master_read_last_time\" declared but not used" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 489 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(509) " "Warning: Verilog HDL assignment warning at rcIII.v(509): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 509 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 rcIII.v(515) " "Warning: Verilog HDL assignment warning at rcIII.v(515): truncated value with size 32 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 515 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "25 1 rcIII.v(521) " "Warning: Verilog HDL assignment warning at rcIII.v(521): truncated value with size 25 to match size of target (1)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 521 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 16 rcIII.v(559) " "Warning: Verilog HDL assignment warning at rcIII.v(559): truncated value with size 32 to match size of target (16)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 559 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(566) " "Warning: Verilog HDL assignment warning at rcIII.v(566): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 566 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 rcIII.v(583) " "Warning: Verilog HDL assignment warning at rcIII.v(583): truncated value with size 32 to match size of target (2)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 583 0 0 } }  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 rcIII.v(600) " "Warning: Verilog HDL assignment warning at rcIII.v(600): truncated value with size 32 to match size of target (8)" {  } { { "rcIII.v" "" { Text "C:/altera/kits/nios2/components/rcIII/system/rcIII.v" 600 0 0 } }  } 0}