rciii.hier_info

niosII基础上实现的嵌入式网络驱动

cpu_0_data_master_writedata[15] => cpu_0_data_master_dbs_write_8~8.DATAB
cpu_0_data_master_writedata[16] => cpu_0_data_master_dbs_write_16~15.DATAB
cpu_0_data_master_writedata[16] => cpu_0_data_master_dbs_write_8~7.DATAB
cpu_0_data_master_writedata[17] => cpu_0_data_master_dbs_write_16~14.DATAB
cpu_0_data_master_writedata[17] => cpu_0_data_master_dbs_write_8~6.DATAB
cpu_0_data_master_writedata[18] => cpu_0_data_master_dbs_write_16~13.DATAB
cpu_0_data_master_writedata[18] => cpu_0_data_master_dbs_write_8~5.DATAB
cpu_0_data_master_writedata[19] => cpu_0_data_master_dbs_write_16~12.DATAB
cpu_0_data_master_writedata[19] => cpu_0_data_master_dbs_write_8~4.DATAB
cpu_0_data_master_writedata[20] => cpu_0_data_master_dbs_write_16~11.DATAB
cpu_0_data_master_writedata[20] => cpu_0_data_master_dbs_write_8~3.DATAB
cpu_0_data_master_writedata[21] => cpu_0_data_master_dbs_write_16~10.DATAB
cpu_0_data_master_writedata[21] => cpu_0_data_master_dbs_write_8~2.DATAB
cpu_0_data_master_writedata[22] => cpu_0_data_master_dbs_write_16~9.DATAB
cpu_0_data_master_writedata[22] => cpu_0_data_master_dbs_write_8~1.DATAB
cpu_0_data_master_writedata[23] => cpu_0_data_master_dbs_write_16~8.DATAB
cpu_0_data_master_writedata[23] => cpu_0_data_master_dbs_write_8~0.DATAB
cpu_0_data_master_writedata[24] => cpu_0_data_master_dbs_write_16~7.DATAB
cpu_0_data_master_writedata[24] => cpu_0_data_master_dbs_write_8~7.DATAA
cpu_0_data_master_writedata[25] => cpu_0_data_master_dbs_write_16~6.DATAB
cpu_0_data_master_writedata[25] => cpu_0_data_master_dbs_write_8~6.DATAA
cpu_0_data_master_writedata[26] => cpu_0_data_master_dbs_write_16~5.DATAB
cpu_0_data_master_writedata[26] => cpu_0_data_master_dbs_write_8~5.DATAA
cpu_0_data_master_writedata[27] => cpu_0_data_master_dbs_write_16~4.DATAB
cpu_0_data_master_writedata[27] => cpu_0_data_master_dbs_write_8~4.DATAA
cpu_0_data_master_writedata[28] => cpu_0_data_master_dbs_write_16~3.DATAB
cpu_0_data_master_writedata[28] => cpu_0_data_master_dbs_write_8~3.DATAA
cpu_0_data_master_writedata[29] => cpu_0_data_master_dbs_write_16~2.DATAB
cpu_0_data_master_writedata[29] => cpu_0_data_master_dbs_write_8~2.DATAA
cpu_0_data_master_writedata[30] => cpu_0_data_master_dbs_write_16~1.DATAB
cpu_0_data_master_writedata[30] => cpu_0_data_master_dbs_write_8~1.DATAA
cpu_0_data_master_writedata[31] => cpu_0_data_master_dbs_write_16~0.DATAB
cpu_0_data_master_writedata[31] => cpu_0_data_master_dbs_write_8~0.DATAA
d1_data_RAM_s1_end_xfer => ~NO_FANOUT~
d1_firmware_ROM_s1_end_xfer => ~NO_FANOUT~
d1_jtag_uart_0_avalon_jtag_slave_end_xfer => ~NO_FANOUT~
d1_payload_buffer_s1_end_xfer => ~NO_FANOUT~
d1_sysid_control_slave_end_xfer => ~NO_FANOUT~
d1_tri_state_bridge_0_avalon_slave_end_xfer => pre_dbs_count_enable~12.IN1
data_RAM_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~0.IN1
data_RAM_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~1.IN1
data_RAM_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~2.IN1
data_RAM_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~3.IN1
data_RAM_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~4.IN1
data_RAM_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~5.IN1
data_RAM_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~6.IN1
data_RAM_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~7.IN1
data_RAM_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~8.IN1
data_RAM_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~9.IN1
data_RAM_s1_readdata_from_sa[10] => cpu_0_data_master_readdata~10.IN1
data_RAM_s1_readdata_from_sa[11] => cpu_0_data_master_readdata~11.IN1
data_RAM_s1_readdata_from_sa[12] => cpu_0_data_master_readdata~12.IN1
data_RAM_s1_readdata_from_sa[13] => cpu_0_data_master_readdata~13.IN1
data_RAM_s1_readdata_from_sa[14] => cpu_0_data_master_readdata~14.IN1
data_RAM_s1_readdata_from_sa[15] => cpu_0_data_master_readdata~15.IN1
data_RAM_s1_readdata_from_sa[16] => cpu_0_data_master_readdata~16.IN1
data_RAM_s1_readdata_from_sa[17] => cpu_0_data_master_readdata~17.IN1
data_RAM_s1_readdata_from_sa[18] => cpu_0_data_master_readdata~18.IN1
data_RAM_s1_readdata_from_sa[19] => cpu_0_data_master_readdata~19.IN1
data_RAM_s1_readdata_from_sa[20] => cpu_0_data_master_readdata~20.IN1
data_RAM_s1_readdata_from_sa[21] => cpu_0_data_master_readdata~21.IN1
data_RAM_s1_readdata_from_sa[22] => cpu_0_data_master_readdata~22.IN1
data_RAM_s1_readdata_from_sa[23] => cpu_0_data_master_readdata~23.IN1
data_RAM_s1_readdata_from_sa[24] => cpu_0_data_master_readdata~24.IN1
data_RAM_s1_readdata_from_sa[25] => cpu_0_data_master_readdata~25.IN1
data_RAM_s1_readdata_from_sa[26] => cpu_0_data_master_readdata~26.IN1
data_RAM_s1_readdata_from_sa[27] => cpu_0_data_master_readdata~27.IN1
data_RAM_s1_readdata_from_sa[28] => cpu_0_data_master_readdata~28.IN1
data_RAM_s1_readdata_from_sa[29] => cpu_0_data_master_readdata~29.IN1
data_RAM_s1_readdata_from_sa[30] => cpu_0_data_master_readdata~30.IN1
data_RAM_s1_readdata_from_sa[31] => cpu_0_data_master_readdata~31.IN1
ext_flash_s1_wait_counter_eq_0 => pre_dbs_count_enable~12.IN0
ext_flash_s1_wait_counter_eq_1 => r_1~23.IN1
firmware_ROM_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~32.IN1
firmware_ROM_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~33.IN1
firmware_ROM_s1_readdata_from_sa[2] => cpu_0_data_master_readdata~34.IN1
firmware_ROM_s1_readdata_from_sa[3] => cpu_0_data_master_readdata~35.IN1
firmware_ROM_s1_readdata_from_sa[4] => cpu_0_data_master_readdata~36.IN1
firmware_ROM_s1_readdata_from_sa[5] => cpu_0_data_master_readdata~37.IN1
firmware_ROM_s1_readdata_from_sa[6] => cpu_0_data_master_readdata~38.IN1
firmware_ROM_s1_readdata_from_sa[7] => cpu_0_data_master_readdata~39.IN1
firmware_ROM_s1_readdata_from_sa[8] => cpu_0_data_master_readdata~40.IN1
firmware_ROM_s1_readdata_from_sa[9] => cpu_0_data_master_readdata~41.IN1
firmware_ROM_s1_readdata_from_sa[10] => cpu_0_data_master_readdata~42.IN1
firmware_ROM_s1_readdata_from_sa[11] => cpu_0_data_master_readdata~43.IN1
firmware_ROM_s1_readdata_from_sa[12] => cpu_0_data_master_readdata~44.IN1
firmware_ROM_s1_readdata_from_sa[13] => cpu_0_data_master_readdata~45.IN1
firmware_ROM_s1_readdata_from_sa[14] => cpu_0_data_master_readdata~46.IN1
firmware_ROM_s1_readdata_from_sa[15] => cpu_0_data_master_readdata~47.IN1
firmware_ROM_s1_readdata_from_sa[16] => cpu_0_data_master_readdata~48.IN1
firmware_ROM_s1_readdata_from_sa[17] => cpu_0_data_master_readdata~49.IN1
firmware_ROM_s1_readdata_from_sa[18] => cpu_0_data_master_readdata~50.IN1
firmware_ROM_s1_readdata_from_sa[19] => cpu_0_data_master_readdata~51.IN1
firmware_ROM_s1_readdata_from_sa[20] => cpu_0_data_master_readdata~52.IN1
firmware_ROM_s1_readdata_from_sa[21] => cpu_0_data_master_readdata~53.IN1
firmware_ROM_s1_readdata_from_sa[22] => cpu_0_data_master_readdata~54.IN1
firmware_ROM_s1_readdata_from_sa[23] => cpu_0_data_master_readdata~55.IN1
firmware_ROM_s1_readdata_from_sa[24] => cpu_0_data_master_readdata~56.IN1
firmware_ROM_s1_readdata_from_sa[25] => cpu_0_data_master_readdata~57.IN1
firmware_ROM_s1_readdata_from_sa[26] => cpu_0_data_master_readdata~58.IN1
firmware_ROM_s1_readdata_from_sa[27] => cpu_0_data_master_readdata~59.IN1
firmware_ROM_s1_readdata_from_sa[28] => cpu_0_data_master_readdata~60.IN1
firmware_ROM_s1_readdata_from_sa[29] => cpu_0_data_master_readdata~61.IN1
firmware_ROM_s1_readdata_from_sa[30] => cpu_0_data_master_readdata~62.IN1
firmware_ROM_s1_readdata_from_sa[31] => cpu_0_data_master_readdata~63.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => cpu_0_data_master_readdata~312.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => dbs_8_reg_segment_0[0].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => dbs_8_reg_segment_1[0].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[0] => dbs_8_reg_segment_2[0].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => cpu_0_data_master_readdata~313.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => dbs_8_reg_segment_0[1].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => dbs_8_reg_segment_1[1].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[1] => dbs_8_reg_segment_2[1].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => cpu_0_data_master_readdata~314.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => dbs_8_reg_segment_0[2].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => dbs_8_reg_segment_1[2].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[2] => dbs_8_reg_segment_2[2].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => cpu_0_data_master_readdata~315.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => dbs_8_reg_segment_0[3].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => dbs_8_reg_segment_1[3].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[3] => dbs_8_reg_segment_2[3].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => cpu_0_data_master_readdata~316.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => dbs_8_reg_segment_0[4].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => dbs_8_reg_segment_1[4].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[4] => dbs_8_reg_segment_2[4].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => cpu_0_data_master_readdata~317.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => dbs_8_reg_segment_0[5].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => dbs_8_reg_segment_1[5].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[5] => dbs_8_reg_segment_2[5].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => cpu_0_data_master_readdata~318.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => dbs_8_reg_segment_0[6].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => dbs_8_reg_segment_1[6].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[6] => dbs_8_reg_segment_2[6].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => cpu_0_data_master_readdata~319.IN1
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => dbs_8_reg_segment_0[7].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => dbs_8_reg_segment_1[7].DATAIN
incoming_tri_state_bridge_0_data_with_Xs_converted_to_0[7] => dbs_8_reg_segment_2[7].DATAIN
jtag_uart_0_avalon_jtag_slave_irq_from_sa => cpu_0_data_master_irq[0].DATAIN
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[0] => p1_registered_cpu_0_data_master_readdata[0].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[1] => p1_registered_cpu_0_data_master_readdata[1].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[2] => p1_registered_cpu_0_data_master_readdata[2].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[3] => p1_registered_cpu_0_data_master_readdata[3].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[4] => p1_registered_cpu_0_data_master_readdata[4].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[5] => p1_registered_cpu_0_data_master_readdata[5].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[6] => p1_registered_cpu_0_data_master_readdata[6].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[7] => p1_registered_cpu_0_data_master_readdata[7].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[8] => p1_registered_cpu_0_data_master_readdata[8].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[9] => p1_registered_cpu_0_data_master_readdata[9].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[10] => p1_registered_cpu_0_data_master_readdata[10].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[11] => p1_registered_cpu_0_data_master_readdata[11].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[12] => p1_registered_cpu_0_data_master_readdata[12].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[13] => p1_registered_cpu_0_data_master_readdata[13].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[14] => p1_registered_cpu_0_data_master_readdata[14].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[15] => p1_registered_cpu_0_data_master_readdata[15].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[16] => p1_registered_cpu_0_data_master_readdata[16].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[17] => p1_registered_cpu_0_data_master_readdata[17].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[18] => p1_registered_cpu_0_data_master_readdata[18].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[19] => p1_registered_cpu_0_data_master_readdata[19].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[20] => p1_registered_cpu_0_data_master_readdata[20].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[21] => p1_registered_cpu_0_data_master_readdata[21].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[22] => p1_registered_cpu_0_data_master_readdata[22].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[23] => p1_registered_cpu_0_data_master_readdata[23].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[24] => p1_registered_cpu_0_data_master_readdata[24].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[25] => p1_registered_cpu_0_data_master_readdata[25].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[26] => p1_registered_cpu_0_data_master_readdata[26].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[27] => p1_registered_cpu_0_data_master_readdata[27].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[28] => p1_registered_cpu_0_data_master_readdata[28].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[29] => p1_registered_cpu_0_data_master_readdata[29].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[30] => p1_registered_cpu_0_data_master_readdata[30].IN1
jtag_uart_0_avalon_jtag_slave_readdata_from_sa[31] => p1_registered_cpu_0_data_master_readdata[31].IN1
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa => r_0~30.IN1
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa => r_0~26.IN1
payload_buffer_s1_readdata_from_sa[0] => cpu_0_data_master_readdata~176.IN1
payload_buffer_s1_readdata_from_sa[0] => dbs_16_reg_segment_0[0].DATAIN
payload_buffer_s1_readdata_from_sa[1] => cpu_0_data_master_readdata~177.IN1