rciii.hif

niosII基础上实现的嵌入式网络驱动

q4
q5
q6
q7
usedw0
usedw1
usedw2
usedw3
usedw4
usedw5
}
# hierarchies {
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo
}
# end
# entity
a_fefifo_7cf
# case_insensitive
# source_file
db|a_fefifo_7cf.tdf
1155807544
6
# storage
db|rcIII.(23).cnf
db|rcIII.(23).cnf
# used_port {
aclr
clock
rreq
sclr
wreq
empty
full
usedw_out0
usedw_out1
usedw_out2
usedw_out3
usedw_out4
usedw_out5
}
# hierarchies {
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state
}
# end
# entity
cntr_rj7
# case_insensitive
# source_file
db|cntr_rj7.tdf
1155807544
6
# storage
db|rcIII.(24).cnf
db|rcIII.(24).cnf
# used_port {
aclr
clock
cnt_en
sclr
updown
q0
q1
q2
q3
q4
q5
}
# hierarchies {
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|a_fefifo_7cf:fifo_state|cntr_rj7:count_usedw
}
# end
# entity
dpram_pcp
# case_insensitive
# source_file
db|dpram_pcp.tdf
1155807544
6
# storage
db|rcIII.(25).cnf
db|rcIII.(25).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
inclock
outclock
outclocken
rdaddress0
rdaddress1
rdaddress2
rdaddress3
rdaddress4
rdaddress5
wraddress0
wraddress1
wraddress2
wraddress3
wraddress4
wraddress5
wren
q0
q1
q2
q3
q4
q5
q6
q7
}
# hierarchies {
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|dpram_pcp:FIFOram
}
# end
# entity
cntr_dl8
# case_insensitive
# source_file
db|cntr_dl8.tdf
1155807544
6
# storage
db|rcIII.(27).cnf
db|rcIII.(27).cnf
# used_port {
aclr
clock
cnt_en
sclr
q0
q1
q2
q3
q4
q5
}
# hierarchies {
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_w:the_jtag_uart_0_scfifo_w|scfifo:wfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:rd_ptr_count
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r|scfifo:rfifo|scfifo_j4p:auto_generated|a_dpfifo_qap:dpfifo|cntr_dl8:wr_ptr
}
# end
# entity
jtag_uart_0_scfifo_r
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
jtag_uart_0.v
1171115330
7
# storage
db|rcIII.(28).cnf
db|rcIII.(28).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rcIII:inst|jtag_uart_0:the_jtag_uart_0|jtag_uart_0_scfifo_r:the_jtag_uart_0_scfifo_r
}
# end
# entity
payload_buffer_s1_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rcIII.v
1171115338
7
# storage
db|rcIII.(30).cnf
db|rcIII.(30).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rcIII:inst|payload_buffer_s1_arbitrator:the_payload_buffer_s1
}
# end
# entity
payload_buffer
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
payload_buffer.v
1171115328
7
# storage
db|rcIII.(31).cnf
db|rcIII.(31).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rcIII:inst|payload_buffer:the_payload_buffer
}
# end
# entity
altsyncram_p111
# case_insensitive
# source_file
db|altsyncram_p111.tdf
1155808024
6
# storage
db|rcIII.(34).cnf
db|rcIII.(34).cnf
# user_parameter {
PORT_A_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_A_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_ADDRESS_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_BYTE_ENABLE_MASK_WIDTH
1
PARAMETER_UNKNOWN
DEF
PORT_B_DATA_WIDTH
1
PARAMETER_UNKNOWN
DEF
}
# used_port {
wren_a
data_a0
data_a1
data_a2
data_a3
data_a4
data_a5
data_a6
data_a7
data_a8
data_a9
data_a10
data_a11
data_a12
data_a13
data_a14
data_a15
address_a0
address_a1
address_a2
address_a3
address_a4
address_a5
address_a6
address_a7
address_a8
address_a9
address_a10
address_a11
address_a12
clock0
clocken0
byteena_a0
byteena_a1
q_a0
q_a1
q_a2
q_a3
q_a4
q_a5
q_a6
q_a7
q_a8
q_a9
q_a10
q_a11
q_a12
q_a13
q_a14
q_a15
}
# memory_file {
payload_buffer.hex
1155807992
}
# hierarchies {
rcIII:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated
}
# end
# entity
decode_1oa
# case_insensitive
# source_file
db|decode_1oa.tdf
1155808024
6
# storage
db|rcIII.(35).cnf
db|rcIII.(35).cnf
# used_port {
data0
enable
eq0
eq1
}
# hierarchies {
rcIII:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:decode3
rcIII:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|decode_1oa:deep_decode
}
# end
# entity
mux_0kb
# case_insensitive
# source_file
db|mux_0kb.tdf
1155808024
6
# storage
db|rcIII.(36).cnf
db|rcIII.(36).cnf
# used_port {
data0
data1
data2
data3
data4
data5
data6
data7
data8
data9
data10
data11
data12
data13
data14
data15
data16
data17
data18
data19
data20
data21
data22
data23
data24
data25
data26
data27
data28
data29
data30
data31
sel0
result0
result1
result2
result3
result4
result5
result6
result7
result8
result9
result10
result11
result12
result13
result14
result15
}
# hierarchies {
rcIII:inst|payload_buffer:the_payload_buffer|altsyncram:the_altsyncram|altsyncram_p111:auto_generated|mux_0kb:mux2
}
# end
# entity
sysid_control_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rcIII.v
1171115338
7
# storage
db|rcIII.(37).cnf
db|rcIII.(37).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rcIII:inst|sysid_control_slave_arbitrator:the_sysid_control_slave
}
# end
# entity
sysid
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
sysid.v
1171115330
7
# storage
db|rcIII.(38).cnf
db|rcIII.(38).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rcIII:inst|sysid:the_sysid
}
# end
# entity
tri_state_bridge_0_avalon_slave_arbitrator
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rcIII.v
1171115338
7
# storage
db|rcIII.(39).cnf
db|rcIII.(39).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rcIII:inst|tri_state_bridge_0_avalon_slave_arbitrator:the_tri_state_bridge_0_avalon_slave
}
# end
# entity
rcIII_reset_clk_domain_synch_module
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
rcIII.v
1171115338
7
# storage
db|rcIII.(40).cnf
db|rcIII.(40).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
rcIII:inst|rcIII_reset_clk_domain_synch_module:rcIII_reset_clk_domain_synch
}
# end
# entity
delay_reset_block
# case_insensitive
# source_file
delay_reset_block.bdf
1155805548
23
# storage
db|rcIII.(41).cnf
db|rcIII.(41).cnf
# hierarchies {
delay_reset_block:inst3
}
# end
# entity
reset_counter
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
reset_counter.v
1155805548
7
# storage
db|rcIII.(43).cnf
db|rcIII.(43).cnf
# internal_option {
ADD_PASS_THROUGH_LOGIC_TO_INFERRED_RAMS
ON
AUTO_RESOURCE_SHARING
OFF
}
# hierarchies {
delay_reset_block:inst3|reset_counter:inst
}
# end
# entity
cntr_vm8
# case_insensitive
# source_file
db|cntr_vm8.tdf
1155807546
6
# storage
db|rcIII.(48).cnf
db|rcIII.(48).cnf
# used_port {
clock
cnt_en
aclr
q0
q1
q2
q3
q4
q5
q6
q7
q8
q9
cout
}
# hierarchies {
delay_reset_block:inst3|reset_counter:inst|lpm_counter:lpm_counter_component|cntr_vm8:auto_generated
}
# end
# entity
decode_rpe
# case_insensitive
# source_file
db|decode_rpe.tdf
1155807550
6
# storage
db|rcIII.(53).cnf
db|rcIII.(53).cnf
# used_port {
aclr
clken
clock
data0
data1
data2
enable
eq0
eq1
eq2
eq3
eq4
eq5
eq6
eq7
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|rcIII.(26).cnf
db|rcIII.(26).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
BIDIR_DUAL_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
5
PARAMETER_DEC
USR
NUMWORDS_A
32
PARAMETER_DEC
USR
OUTDATA_REG_A
UNREGISTERED
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
INDATA_ACLR_A
NONE
PARAMETER_UNKNOWN
USR
BYTEENA_ACLR_A
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_B
32
PARAMETER_DEC
USR
WIDTHAD_B
5
PARAMETER_DEC
USR
NUMWORDS_B
32
PARAMETER_DEC
USR
INDATA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
WRCONTROL_WRADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
RDCONTROL_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
ADDRESS_REG_B
CLOCK1
PARAMETER_UNKNOWN
USR
OUTDATA_REG_B
UNREGISTERED
PARAMETER_UNKNOWN
USR
BYTEENA_REG_B
CLOCK1
PARAMETER_UNKNOWN
DEF
INDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
WRCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
ADDRESS_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
OUTDATA_ACLR_B
NONE
PARAMETER_UNKNOWN
USR
RDCONTROL_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
BYTEENA_ACLR_B
NONE
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_A
1
PARAMETER_UNKNOWN
DEF
WIDTH_BYTEENA_B
1
PARAMETER_UNKNOWN
DEF
RAM_BLOCK_TYPE
AUTO
PARAMETER_UNKNOWN
USR
BYTE_SIZE
8
PARAMETER_UNKNOWN
DEF
READ_DURING_WRITE_MODE_MIXED_PORTS
OLD_DATA
PARAMETER_UNKNOWN
USR
INIT_FILE
rf_ram.mif
PARAMETER_UNKNOWN
USR
INIT_FILE_LAYOUT
PORT_A
PARAMETER_UNKNOWN
DEF
MAXIMUM_DEPTH
0
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_INPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_A
NORMAL
PARAMETER_UNKNOWN
DEF
CLOCK_ENABLE_OUTPUT_B
NORMAL
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone II
PARAMETER_UNKNOWN
USR
CBXI_PARAMETER
altsyncram_vuo1
PARAMETER_UNKNOWN
USR
}
# used_port {
address_a
address_a
address_a
address_a
address_a
address_b
address_b
address_b
address_b
address_b
clock0
clock1
clocken0
clocken1
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_a
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
data_b
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_a
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
q_b
wren_a
wren_b
}
# include_file {
..|..|..|..|..|quartus50|libraries|megafunctions|stratix_ram_block.inc
1107575592
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_mux.inc
1107574776
..|..|..|..|..|quartus50|libraries|megafunctions|lpm_decode.inc
1107574570
..|..|..|..|..|quartus50|libraries|megafunctions|aglobal50.inc
1131033050
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.inc
1107573506
..|..|..|..|..|quartus50|libraries|megafunctions|a_rdenreg.inc
1107572148
..|..|..|..|..|quartus50|libraries|megafunctions|altrom.inc
1107573422
..|..|..|..|..|quartus50|libraries|megafunctions|altram.inc
1107573384
..|..|..|..|..|quartus50|libraries|megafunctions|altdpram.inc
1107573082
..|..|..|..|..|quartus50|libraries|megafunctions|altqpram.inc
1107573362
}
# hierarchies {
rcIII:inst|cpu_0:the_cpu_0|cpu_0_rf_module:cpu_0_rf|altsyncram:the_altsyncram
}
# end
# entity
altsyncram
# case_insensitive
# source_file
..|..|..|..|..|quartus50|libraries|megafunctions|altsyncram.tdf
1114012438
6
# storage
db|rcIII.(54).cnf
db|rcIII.(54).cnf
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
OPERATION_MODE
SINGLE_PORT
PARAMETER_UNKNOWN
USR
WIDTH_A
32
PARAMETER_DEC
USR
WIDTHAD_A
8
PARAMETER_DEC
USR
NUMWORDS_A
256