scfifo_j4p.tdf

niosII基础上实现的嵌入式网络驱动

--scfifo DEVICE_FAMILY="Cyclone II" LPM_NUMWORDS=64 LPM_SHOWAHEAD="OFF" lpm_width=8 lpm_widthu=6 OPTIMIZE_FOR_SPEED=5 OVERFLOW_CHECKING="OFF" UNDERFLOW_CHECKING="OFF" USE_EAB="ON" clock data empty full q rdreq usedw wrreq lpm_hint="RAM_BLOCK_TYPE=AUTO" RAM_BLOCK_TYPE="AUTO"
--VERSION_BEGIN 5.0 cbx_altdpram 2004:11:30:11:29:56:SJ cbx_altsyncram 2005:11:01:19:33:48:SJ cbx_cycloneii 2004:12:20:14:28:52:SJ cbx_fifo_common 2004:12:13:14:26:24:SJ cbx_lpm_add_sub 2005:04:12:13:30:42:SJ cbx_lpm_compare 2004:11:30:11:30:40:SJ cbx_lpm_counter 2005:02:02:04:37:10:SJ cbx_lpm_decode 2004:12:13:14:19:12:SJ cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:05:19:13:51:58:SJ cbx_scfifo 2005:03:10:10:52:20:SJ cbx_stratix 2005:11:01:14:36:46:SJ cbx_stratixii 2004:12:22:13:27:12:SJ cbx_util_mgl 2005:04:04:13:50:06:SJ  VERSION_END


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FUNCTION a_dpfifo_qap (clock, data[7..0], rreq, sclr, wreq)
RETURNS ( empty, full, q[7..0], usedw[5..0]);

--synthesis_resources = lut 14 M4K 1 reg 12 
SUBDESIGN scfifo_j4p
( 
	clock	:	input;
	data[7..0]	:	input;
	empty	:	output;
	full	:	output;
	q[7..0]	:	output;
	rdreq	:	input;
	usedw[5..0]	:	output;
	wrreq	:	input;
) 
VARIABLE 
	dpfifo : a_dpfifo_qap;
	sclr	: NODE;

BEGIN 
	dpfifo.clock = clock;
	dpfifo.data[] = data[];
	dpfifo.rreq = rdreq;
	dpfifo.sclr = sclr;
	dpfifo.wreq = wrreq;
	empty = dpfifo.empty;
	full = dpfifo.full;
	q[] = dpfifo.q[];
	sclr = GND;
	usedw[] = dpfifo.usedw[];
END;
--VALID FILE