led.tan.qmsg

来自「用VHDL开发的数字钟资料 完整的实验代码」· QMSG 代码 · 共 16 行 · 第 1/4 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "b1\[0\] " "Warning: Node \"b1\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c\[0\] " "Warning: Node \"c\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b1\[1\] " "Warning: Node \"b1\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c\[1\] " "Warning: Node \"c\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b1\[2\] " "Warning: Node \"b1\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c\[2\] " "Warning: Node \"c\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b1\[3\] " "Warning: Node \"b1\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c\[3\] " "Warning: Node \"c\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b1\[4\] " "Warning: Node \"b1\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c\[4\] " "Warning: Node \"c\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b1\[5\] " "Warning: Node \"b1\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c\[5\] " "Warning: Node \"c\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b\[6\] " "Warning: Node \"b\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c1\[6\] " "Warning: Node \"c1\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d1\[6\] " "Warning: Node \"d1\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b1\[6\] " "Warning: Node \"b1\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 22 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d\[6\] " "Warning: Node \"d\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c\[6\] " "Warning: Node \"c\[6\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d\[0\] " "Warning: Node \"d\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d1\[0\] " "Warning: Node \"d1\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b\[0\] " "Warning: Node \"b\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c1\[0\] " "Warning: Node \"c1\[0\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d\[1\] " "Warning: Node \"d\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d1\[1\] " "Warning: Node \"d1\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b\[1\] " "Warning: Node \"b\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c1\[1\] " "Warning: Node \"c1\[1\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d\[2\] " "Warning: Node \"d\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d1\[2\] " "Warning: Node \"d1\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b\[2\] " "Warning: Node \"b\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c1\[2\] " "Warning: Node \"c1\[2\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d\[3\] " "Warning: Node \"d\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d1\[3\] " "Warning: Node \"d1\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b\[3\] " "Warning: Node \"b\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c1\[3\] " "Warning: Node \"c1\[3\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d\[4\] " "Warning: Node \"d\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d1\[4\] " "Warning: Node \"d1\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b\[4\] " "Warning: Node \"b\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c1\[4\] " "Warning: Node \"c1\[4\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d\[5\] " "Warning: Node \"d\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 25 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "d1\[5\] " "Warning: Node \"d1\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "b\[5\] " "Warning: Node \"b\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 21 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "c1\[5\] " "Warning: Node \"c1\[5\]\" is a latch" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 24 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 8 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "s1\[3\] " "Info: Assuming node \"s1\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 10 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "s1\[2\] " "Info: Assuming node \"s1\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 10 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "s1\[1\] " "Info: Assuming node \"s1\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 10 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "m\[3\] " "Info: Assuming node \"m\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "m\[2\] " "Info: Assuming node \"m\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "m\[1\] " "Info: Assuming node \"m\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "s\[3\] " "Info: Assuming node \"s\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 9 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "s\[2\] " "Info: Assuming node \"s\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 9 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "s\[1\] " "Info: Assuming node \"s\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 9 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "m1\[3\] " "Info: Assuming node \"m1\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 12 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "m1\[2\] " "Info: Assuming node \"m1\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 12 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "m1\[1\] " "Info: Assuming node \"m1\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 12 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h1\[3\] " "Info: Assuming node \"h1\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h1\[2\] " "Info: Assuming node \"h1\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h1\[1\] " "Info: Assuming node \"h1\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h\[3\] " "Info: Assuming node \"h\[3\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 13 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h\[2\] " "Info: Assuming node \"h\[2\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 13 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_SPECIAL_CLK" "h\[1\] " "Info: Assuming node \"h\[1\]\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 13 -1 0 } }  } 0 0 "Assuming node \"%1!s!\" is a latch enable and/or memory write/read enable. Will not compute fmax for this pin." 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}