led.tan.qmsg

来自「用VHDL开发的数字钟资料 完整的实验代码」· QMSG 代码 · 共 16 行 · 第 1/4 页

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "Mux40~32 " "Info: Detected gated clock \"Mux40~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 63 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux40~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "Mux48~32 " "Info: Detected gated clock \"Mux48~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 50 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux48~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "Mux9~32 " "Info: Detected gated clock \"Mux9~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 121 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux9~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "Mux32~32 " "Info: Detected gated clock \"Mux32~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 79 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux32~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "Mux24~32 " "Info: Detected gated clock \"Mux24~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 92 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux24~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_GATED_CLK" "Mux16~32 " "Info: Detected gated clock \"Mux16~32\" as buffer" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 108 -1 0 } } { "e:/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/quartus/bin/Assignment Editor.qase" 1 { { 0 "Mux16~32" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clk register register a\[0\] a\[2\] 125.0 MHz Internal " "Info: Clock \"clk\" Internal fmax is restricted to 125.0 MHz between source register \"a\[0\]\" and destination register \"a\[2\]\"" { { "Info" "ITDB_CLOCK_TCH_TCL" "4.0 ns 4.0 ns 8.0 ns " "Info: fmax restricted to Clock High delay (4.0 ns) plus Clock Low delay (4.0 ns) : restricted to 8.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.000 ns + Longest register register " "Info: + Longest register to register delay is 4.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns a\[0\] 1 REG LC3_B15 15 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_B15; Fanout = 15; REG Node = 'a\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[0] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.300 ns) + CELL(1.700 ns) 4.000 ns a\[2\] 2 REG LC6_B24 14 " "Info: 2: + IC(2.300 ns) + CELL(1.700 ns) = 4.000 ns; Loc. = LC6_B24; Fanout = 14; REG Node = 'a\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { a[0] a[2] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.700 ns ( 42.50 % ) " "Info: Total cell delay = 1.700 ns ( 42.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.300 ns ( 57.50 % ) " "Info: Total interconnect delay = 2.300 ns ( 57.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { a[0] a[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "4.000 ns" { a[0] {} a[2] {} } { 0.000ns 2.300ns } { 0.000ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 5.300 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 3 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns a\[2\] 2 REG LC6_B24 14 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC6_B24; Fanout = 14; REG Node = 'a\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk a[2] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk a[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} a[2] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 5.300 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 5.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns clk 1 CLK PIN_43 3 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_43; Fanout = 3; CLK Node = 'clk'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.500 ns) + CELL(0.000 ns) 5.300 ns a\[0\] 2 REG LC3_B15 15 " "Info: 2: + IC(2.500 ns) + CELL(0.000 ns) = 5.300 ns; Loc. = LC3_B15; Fanout = 15; REG Node = 'a\[0\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.500 ns" { clk a[0] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 30 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.800 ns ( 52.83 % ) " "Info: Total cell delay = 2.800 ns ( 52.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.500 ns ( 47.17 % ) " "Info: Total interconnect delay = 2.500 ns ( 47.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk a[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} a[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk a[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} a[2] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk a[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} a[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "2.500 ns + " "Info: + Micro setup delay of destination is 2.500 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 30 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.000 ns" { a[0] a[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "4.000 ns" { a[0] {} a[2] {} } { 0.000ns 2.300ns } { 0.000ns 1.700ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk a[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} a[2] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { clk a[0] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "5.300 ns" { clk {} clk~out {} a[0] {} } { 0.000ns 0.000ns 2.500ns } { 0.000ns 2.800ns 0.000ns } "" } }  } 0 0 "fmax restricted to Clock High delay (%1!s!) plus Clock Low delay (%2!s!) : restricted to %3!s!. Expand message to see actual delay path." 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { a[2] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "" { a[2] {} } {  } {  } "" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 30 -1 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "c\[3\] m\[3\] m\[2\] 6.500 ns register " "Info: tsu for register \"c\[3\]\" (data pin = \"m\[3\]\", clock pin = \"m\[2\]\") is 6.500 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "13.200 ns + Longest pin register " "Info: + Longest pin to register delay is 13.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns m\[3\] 1 CLK PIN_36 5 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_36; Fanout = 5; CLK Node = 'm\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[3] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(1.800 ns) 8.700 ns Mux27~9 2 COMB LC4_B3 1 " "Info: 2: + IC(3.400 ns) + CELL(1.800 ns) = 8.700 ns; Loc. = LC4_B3; Fanout = 1; COMB Node = 'Mux27~9'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.200 ns" { m[3] Mux27~9 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.200 ns) + CELL(2.300 ns) 13.200 ns c\[3\] 3 REG LC2_B4 1 " "Info: 3: + IC(2.200 ns) + CELL(2.300 ns) = 13.200 ns; Loc. = LC2_B4; Fanout = 1; REG Node = 'c\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Mux27~9 c[3] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns ( 57.58 % ) " "Info: Total cell delay = 7.600 ns ( 57.58 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.600 ns ( 42.42 % ) " "Info: Total interconnect delay = 5.600 ns ( 42.42 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "13.200 ns" { m[3] Mux27~9 c[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "13.200 ns" { m[3] {} m[3]~out {} Mux27~9 {} c[3] {} } { 0.000ns 0.000ns 3.400ns 2.200ns } { 0.000ns 3.500ns 1.800ns 2.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.700 ns + " "Info: + Micro setup delay of destination is 4.700 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "m\[2\] destination 11.400 ns - Shortest register " "Info: - Shortest clock path from clock \"m\[2\]\" to destination register is 11.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.800 ns) 2.800 ns m\[2\] 1 CLK PIN_42 8 " "Info: 1: + IC(0.000 ns) + CELL(2.800 ns) = 2.800 ns; Loc. = PIN_42; Fanout = 8; CLK Node = 'm\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { m[2] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.500 ns) + CELL(2.300 ns) 6.600 ns Mux24~32 2 COMB LC2_B3 7 " "Info: 2: + IC(1.500 ns) + CELL(2.300 ns) = 6.600 ns; Loc. = LC2_B3; Fanout = 7; COMB Node = 'Mux24~32'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "3.800 ns" { m[2] Mux24~32 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 92 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.800 ns) 11.400 ns c\[3\] 3 REG LC2_B4 1 " "Info: 3: + IC(3.000 ns) + CELL(1.800 ns) = 11.400 ns; Loc. = LC2_B4; Fanout = 1; REG Node = 'c\[3\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { Mux24~32 c[3] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.900 ns ( 60.53 % ) " "Info: Total cell delay = 6.900 ns ( 60.53 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 39.47 % ) " "Info: Total interconnect delay = 4.500 ns ( 39.47 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "11.400 ns" { m[2] Mux24~32 c[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "11.400 ns" { m[2] {} m[2]~out {} Mux24~32 {} c[3] {} } { 0.000ns 0.000ns 1.500ns 3.000ns } { 0.000ns 2.800ns 2.300ns 1.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "13.200 ns" { m[3] Mux27~9 c[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "13.200 ns" { m[3] {} m[3]~out {} Mux27~9 {} c[3] {} } { 0.000ns 0.000ns 3.400ns 2.200ns } { 0.000ns 3.500ns 1.800ns 2.300ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "11.400 ns" { m[2] Mux24~32 c[3] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "11.400 ns" { m[2] {} m[2]~out {} Mux24~32 {} c[3] {} } { 0.000ns 0.000ns 1.500ns 3.000ns } { 0.000ns 2.800ns 2.300ns 1.800ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "h1\[1\] led7\[6\] d1\[6\] 29.300 ns register " "Info: tco from clock \"h1\[1\]\" to destination pin \"led7\[6\]\" through register \"d1\[6\]\" is 29.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "h1\[1\] source 14.500 ns + Longest register " "Info: + Longest clock path from clock \"h1\[1\]\" to source register is 14.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns h1\[1\] 1 CLK PIN_72 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_72; Fanout = 8; CLK Node = 'h1\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { h1[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(2.300 ns) 9.800 ns Mux48~32 2 COMB LC2_A2 7 " "Info: 2: + IC(4.000 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC2_A2; Fanout = 7; COMB Node = 'Mux48~32'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { h1[1] Mux48~32 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(1.800 ns) 14.500 ns d1\[6\] 3 REG LC7_A8 1 " "Info: 3: + IC(2.900 ns) + CELL(1.800 ns) = 14.500 ns; Loc. = LC7_A8; Fanout = 1; REG Node = 'd1\[6\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.700 ns" { Mux48~32 d1[6] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns ( 52.41 % ) " "Info: Total cell delay = 7.600 ns ( 52.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.900 ns ( 47.59 % ) " "Info: Total interconnect delay = 6.900 ns ( 47.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { h1[1] Mux48~32 d1[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { h1[1] {} h1[1]~out {} Mux48~32 {} d1[6] {} } { 0.000ns 0.000ns 4.000ns 2.900ns } { 0.000ns 3.500ns 2.300ns 1.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "14.800 ns + Longest register pin " "Info: + Longest register to pin delay is 14.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns d1\[6\] 1 REG LC7_A8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC7_A8; Fanout = 1; REG Node = 'd1\[6\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { d1[6] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(2.300 ns) 5.800 ns Mux1~337 2 COMB LC2_B15 1 " "Info: 2: + IC(3.500 ns) + CELL(2.300 ns) = 5.800 ns; Loc. = LC2_B15; Fanout = 1; COMB Node = 'Mux1~337'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "5.800 ns" { d1[6] Mux1~337 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 8.700 ns Mux1~340 3 COMB LC7_B15 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 8.700 ns; Loc. = LC7_B15; Fanout = 1; COMB Node = 'Mux1~340'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { Mux1~337 Mux1~340 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(5.100 ns) 14.800 ns led7\[6\] 4 PIN PIN_49 0 " "Info: 4: + IC(1.000 ns) + CELL(5.100 ns) = 14.800 ns; Loc. = PIN_49; Fanout = 0; PIN Node = 'led7\[6\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { Mux1~340 led7[6] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 16 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "9.700 ns ( 65.54 % ) " "Info: Total cell delay = 9.700 ns ( 65.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.100 ns ( 34.46 % ) " "Info: Total interconnect delay = 5.100 ns ( 34.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { d1[6] Mux1~337 Mux1~340 led7[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { d1[6] {} Mux1~337 {} Mux1~340 {} led7[6] {} } { 0.000ns 3.500ns 0.600ns 1.000ns } { 0.000ns 2.300ns 2.300ns 5.100ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.500 ns" { h1[1] Mux48~32 d1[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.500 ns" { h1[1] {} h1[1]~out {} Mux48~32 {} d1[6] {} } { 0.000ns 0.000ns 4.000ns 2.900ns } { 0.000ns 3.500ns 2.300ns 1.800ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.800 ns" { d1[6] Mux1~337 Mux1~340 led7[6] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.800 ns" { d1[6] {} Mux1~337 {} Mux1~340 {} led7[6] {} } { 0.000ns 3.500ns 0.600ns 1.000ns } { 0.000ns 2.300ns 2.300ns 5.100ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}