led.tan.qmsg

来自「用VHDL开发的数字钟资料 完整的实验代码」· QMSG 代码 · 共 16 行 · 第 1/4 页

{ "Info" "ITDB_TH_RESULT" "d1\[1\] h1\[2\] h1\[1\] 3.100 ns register " "Info: th for register \"d1\[1\]\" (data pin = \"h1\[2\]\", clock pin = \"h1\[1\]\") is 3.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "h1\[1\] destination 14.300 ns + Longest register " "Info: + Longest clock path from clock \"h1\[1\]\" to destination register is 14.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns h1\[1\] 1 CLK PIN_72 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_72; Fanout = 8; CLK Node = 'h1\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { h1[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.000 ns) + CELL(2.300 ns) 9.800 ns Mux48~32 2 COMB LC2_A2 7 " "Info: 2: + IC(4.000 ns) + CELL(2.300 ns) = 9.800 ns; Loc. = LC2_A2; Fanout = 7; COMB Node = 'Mux48~32'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "6.300 ns" { h1[1] Mux48~32 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.700 ns) + CELL(1.800 ns) 14.300 ns d1\[1\] 3 REG LC1_A5 1 " "Info: 3: + IC(2.700 ns) + CELL(1.800 ns) = 14.300 ns; Loc. = LC1_A5; Fanout = 1; REG Node = 'd1\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { Mux48~32 d1[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns ( 53.15 % ) " "Info: Total cell delay = 7.600 ns ( 53.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.700 ns ( 46.85 % ) " "Info: Total interconnect delay = 6.700 ns ( 46.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.300 ns" { h1[1] Mux48~32 d1[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.300 ns" { h1[1] {} h1[1]~out {} Mux48~32 {} d1[1] {} } { 0.000ns 0.000ns 4.000ns 2.700ns } { 0.000ns 3.500ns 2.300ns 1.800ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.200 ns - Shortest pin register " "Info: - Shortest pin to register delay is 11.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.500 ns) 3.500 ns h1\[2\] 1 CLK PIN_17 8 " "Info: 1: + IC(0.000 ns) + CELL(3.500 ns) = 3.500 ns; Loc. = PIN_17; Fanout = 8; CLK Node = 'h1\[2\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "" { h1[2] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(1.800 ns) 8.300 ns Mux49~32 2 COMB LC6_A5 1 " "Info: 2: + IC(3.000 ns) + CELL(1.800 ns) = 8.300 ns; Loc. = LC6_A5; Fanout = 1; COMB Node = 'Mux49~32'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "4.800 ns" { h1[2] Mux49~32 } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(2.300 ns) 11.200 ns d1\[1\] 3 REG LC1_A5 1 " "Info: 3: + IC(0.600 ns) + CELL(2.300 ns) = 11.200 ns; Loc. = LC1_A5; Fanout = 1; REG Node = 'd1\[1\]'" {  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { Mux49~32 d1[1] } "NODE_NAME" } } { "led.vhd" "" { Text "G:/edatest/yulin/yulin/clock/led/led.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.600 ns ( 67.86 % ) " "Info: Total cell delay = 7.600 ns ( 67.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.600 ns ( 32.14 % ) " "Info: Total interconnect delay = 3.600 ns ( 32.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "11.200 ns" { h1[2] Mux49~32 d1[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "11.200 ns" { h1[2] {} h1[2]~out {} Mux49~32 {} d1[1] {} } { 0.000ns 0.000ns 3.000ns 0.600ns } { 0.000ns 3.500ns 1.800ns 2.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "14.300 ns" { h1[1] Mux48~32 d1[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "14.300 ns" { h1[1] {} h1[1]~out {} Mux48~32 {} d1[1] {} } { 0.000ns 0.000ns 4.000ns 2.700ns } { 0.000ns 3.500ns 2.300ns 1.800ns } "" } } { "e:/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/quartus/bin/TimingClosureFloorplan.fld" "" "11.200 ns" { h1[2] Mux49~32 d1[1] } "NODE_NAME" } } { "e:/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/quartus/bin/Technology_Viewer.qrui" "11.200 ns" { h1[2] {} h1[2]~out {} Mux49~32 {} d1[1] {} } { 0.000ns 0.000ns 3.000ns 0.600ns } { 0.000ns 3.500ns 1.800ns 2.300ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_UNUSED" "" "Info: Parallel compilation was enabled but no parallel operations were performed" {  } {  } 0 0 "Parallel compilation was enabled but no parallel operations were performed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 45 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 45 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "125 " "Info: Peak virtual memory: 125 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Apr 22 22:20:16 2009 " "Info: Processing ended: Wed Apr 22 22:20:16 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}