vhdl1.map.qmsg

基于vhdl的数字钟完整工程文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 18 23:13:29 2007 " "Info: Processing started: Sun Nov 18 23:13:29 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Vhdl1 -c Vhdl1 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Vhdl1 -c Vhdl1" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Vhdl1.vhd 6 3 " "Info: Found 6 design units, including 3 entities, in source file Vhdl1.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 count-behav " "Info: Found design unit 1: count-behav" {  } { { "Vhdl1.vhd" "" { Text "E:/software/shuzizhong/Vhdl1.vhd" 13 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 s_machine-behav " "Info: Found design unit 2: s_machine-behav" {  } { { "Vhdl1.vhd" "" { Text "E:/software/shuzizhong/Vhdl1.vhd" 43 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 freq_d10-behav " "Info: Found design unit 3: freq_d10-behav" {  } { { "Vhdl1.vhd" "" { Text "E:/software/shuzizhong/Vhdl1.vhd" 73 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 count " "Info: Found entity 1: count" {  } { { "Vhdl1.vhd" "" { Text "E:/software/shuzizhong/Vhdl1.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 s_machine " "Info: Found entity 2: s_machine" {  } { { "Vhdl1.vhd" "" { Text "E:/software/shuzizhong/Vhdl1.vhd" 38 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 freq_d10 " "Info: Found entity 3: freq_d10" {  } { { "Vhdl1.vhd" "" { Text "E:/software/shuzizhong/Vhdl1.vhd" 68 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Error" "ESGN_TOP_ENTITY_IS_MISSING" "Vhdl1 " "Error: Top-level design entity \"Vhdl1\" is undefined" {  } {  } 0 0 "Top-level design entity \"%1!s!\" is undefined" 0 0 "" 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 1  0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 1 error, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "145 " "Info: Allocated 145 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun Nov 18 23:13:31 2007 " "Error: Processing ended: Sun Nov 18 23:13:31 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:02 " "Error: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}