prev_cmp_plj.map.qmsg

基于vhdl 的数字频率计的设计源程序及工程文件

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 156 04/30/2007 SJ Full Version " "Info: Version 7.1 Build 156 04/30/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Dec 17 01:24:26 2007 " "Info: Processing started: Mon Dec 17 01:24:26 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off plj -c plj " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off plj -c plj" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "plj.vhd 10 5 " "Info: Found 10 design units, including 5 entities, in source file plj.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 fen-rtl " "Info: Found design unit 1: fen-rtl" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 8 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "2 pilvji-rtl " "Info: Found design unit 2: pilvji-rtl" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 45 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "3 lock-rtl " "Info: Found design unit 3: lock-rtl" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 107 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "4 ch-rtl " "Info: Found design unit 4: ch-rtl" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 127 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_DESIGN_UNIT_NAME" "5 plj-rtl " "Info: Found design unit 5: plj-rtl" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 158 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 fen " "Info: Found entity 1: fen" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 4 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 pilvji " "Info: Found entity 2: pilvji" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 40 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 lock " "Info: Found entity 3: lock" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 102 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 ch " "Info: Found entity 4: ch" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 120 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 plj " "Info: Found entity 5: plj" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 151 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "plj " "Info: Elaborating entity \"plj\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "fen fen:u1 " "Info: Elaborating entity \"fen\" for hierarchy \"fen:u1\"" {  } { { "plj.vhd" "u1" { Text "N:/eda/plj6/plj.vhd" 183 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pilvji pilvji:u2 " "Info: Elaborating entity \"pilvji\" for hierarchy \"pilvji:u2\"" {  } { { "plj.vhd" "u2" { Text "N:/eda/plj6/plj.vhd" 184 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lock lock:u3 " "Info: Elaborating entity \"lock\" for hierarchy \"lock:u3\"" {  } { { "plj.vhd" "u3" { Text "N:/eda/plj6/plj.vhd" 185 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ch ch:u4 " "Info: Elaborating entity \"ch\" for hierarchy \"ch:u4\"" {  } { { "plj.vhd" "u4" { Text "N:/eda/plj6/plj.vhd" 186 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "e0 plj.vhd(138) " "Warning (10492): VHDL Process Statement warning at plj.vhd(138): signal \"e0\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 138 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dian plj.vhd(138) " "Warning (10492): VHDL Process Statement warning at plj.vhd(138): signal \"dian\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 138 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "e1 plj.vhd(139) " "Warning (10492): VHDL Process Statement warning at plj.vhd(139): signal \"e1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 139 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dian plj.vhd(139) " "Warning (10492): VHDL Process Statement warning at plj.vhd(139): signal \"dian\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 139 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "e2 plj.vhd(140) " "Warning (10492): VHDL Process Statement warning at plj.vhd(140): signal \"e2\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 140 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dian plj.vhd(140) " "Warning (10492): VHDL Process Statement warning at plj.vhd(140): signal \"dian\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 140 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "e3 plj.vhd(141) " "Warning (10492): VHDL Process Statement warning at plj.vhd(141): signal \"e3\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 141 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dian plj.vhd(141) " "Warning (10492): VHDL Process Statement warning at plj.vhd(141): signal \"dian\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 141 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "dang1 plj.vhd(142) " "Warning (10492): VHDL Process Statement warning at plj.vhd(142): signal \"dang1\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 142 0 0 } }  } 0 10492 "VHDL Process Statement warning at %2!s!: signal \"%1!s!\" is read inside the Process Statement but isn't in the Process Statement's sensitivity list" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "tmp plj.vhd(135) " "Warning (10631): VHDL Process Statement warning at plj.vhd(135): inferring latch(es) for signal or variable \"tmp\", which holds its previous value in one or more paths through the process" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Warning" "WVRFX_L2_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "nod plj.vhd(135) " "Warning (10631): VHDL Process Statement warning at plj.vhd(135): inferring latch(es) for signal or variable \"nod\", which holds its previous value in one or more paths through the process" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "nod plj.vhd(135) " "Info (10041): Inferred latch for \"nod\" at plj.vhd(135)" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tmp\[0\] plj.vhd(135) " "Info (10041): Inferred latch for \"tmp\[0\]\" at plj.vhd(135)" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tmp\[1\] plj.vhd(135) " "Info (10041): Inferred latch for \"tmp\[1\]\" at plj.vhd(135)" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tmp\[2\] plj.vhd(135) " "Info (10041): Inferred latch for \"tmp\[2\]\" at plj.vhd(135)" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "tmp\[3\] plj.vhd(135) " "Info (10041): Inferred latch for \"tmp\[3\]\" at plj.vhd(135)" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 0 0 } }  } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "" 0}