prev_cmp_plj.tan.qmsg

基于vhdl 的数字频率计的设计源程序及工程文件

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lock:u3\|m5\[1\] register ch:u4\|nod 24.04 MHz 41.6 ns Internal " "Info: Clock \"clk\" has Internal fmax of 24.04 MHz between source register \"lock:u3\|m5\[1\]\" and destination register \"ch:u4\|nod\" (period= 41.6 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register register " "Info: + Longest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lock:u3\|m5\[1\] 1 REG LC3_D32 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_D32; Fanout = 1; REG Node = 'lock:u3\|m5\[1\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lock:u3|m5[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 2.100 ns ch:u4\|Mux0~93 2 COMB LC4_D32 1 " "Info: 2: + IC(0.200 ns) + CELL(1.900 ns) = 2.100 ns; Loc. = LC4_D32; Fanout = 1; COMB Node = 'ch:u4\|Mux0~93'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lock:u3|m5[1] ch:u4|Mux0~93 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.000 ns ch:u4\|Mux0~94 3 COMB LC6_D32 1 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.000 ns; Loc. = LC6_D32; Fanout = 1; COMB Node = 'ch:u4\|Mux0~94'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { ch:u4|Mux0~93 ch:u4|Mux0~94 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 5.900 ns ch:u4\|nod 4 REG LC7_D32 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 5.900 ns; Loc. = LC7_D32; Fanout = 1; REG Node = 'ch:u4\|nod'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { ch:u4|Mux0~94 ch:u4|nod } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 124 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 89.83 % ) " "Info: Total cell delay = 5.300 ns ( 89.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 10.17 % ) " "Info: Total interconnect delay = 0.600 ns ( 10.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { lock:u3|m5[1] ch:u4|Mux0~93 ch:u4|Mux0~94 ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { lock:u3|m5[1] ch:u4|Mux0~93 ch:u4|Mux0~94 ch:u4|nod } { 0.000ns 0.200ns 0.200ns 0.200ns } { 0.000ns 1.900ns 1.700ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-9.700 ns - Smallest " "Info: - Smallest clock skew is -9.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.900 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 14 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(1.100 ns) 8.700 ns ch:u4\|sel\[2\] 2 REG LC3_D35 8 " "Info: 2: + IC(4.500 ns) + CELL(1.100 ns) = 8.700 ns; Loc. = LC3_D35; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.000 ns) 11.900 ns ch:u4\|nod 3 REG LC7_D32 1 " "Info: 3: + IC(1.200 ns) + CELL(2.000 ns) = 11.900 ns; Loc. = LC7_D32; Fanout = 1; REG Node = 'ch:u4\|nod'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 124 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.200 ns ( 52.10 % ) " "Info: Total cell delay = 6.200 ns ( 52.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.700 ns ( 47.90 % ) " "Info: Total interconnect delay = 5.700 ns ( 47.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.900 ns" { clk ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.900 ns" { clk clk~out ch:u4|sel[2] ch:u4|nod } { 0.000ns 0.000ns 4.500ns 1.200ns } { 0.000ns 3.100ns 1.100ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 21.600 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 21.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 14 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(1.100 ns) 8.700 ns fen:u1\|cq 2 REG LC1_D45 29 " "Info: 2: + IC(4.500 ns) + CELL(1.100 ns) = 8.700 ns; Loc. = LC1_D45; Fanout = 29; REG Node = 'fen:u1\|cq'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { clk fen:u1|cq } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(6.300 ns) + CELL(1.100 ns) 16.100 ns fen:u1\|dq 3 REG LC6_J8 63 " "Info: 3: + IC(6.300 ns) + CELL(1.100 ns) = 16.100 ns; Loc. = LC6_J8; Fanout = 63; REG Node = 'fen:u1\|dq'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { fen:u1|cq fen:u1|dq } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(5.500 ns) + CELL(0.000 ns) 21.600 ns lock:u3\|m5\[1\] 4 REG LC3_D32 1 " "Info: 4: + IC(5.500 ns) + CELL(0.000 ns) = 21.600 ns; Loc. = LC3_D32; Fanout = 1; REG Node = 'lock:u3\|m5\[1\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 24.54 % ) " "Info: Total cell delay = 5.300 ns ( 24.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "16.300 ns ( 75.46 % ) " "Info: Total interconnect delay = 16.300 ns ( 75.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "21.600 ns" { clk fen:u1|cq fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "21.600 ns" { clk clk~out fen:u1|cq fen:u1|dq lock:u3|m5[1] } { 0.000ns 0.000ns 4.500ns 6.300ns 5.500ns } { 0.000ns 3.100ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.900 ns" { clk ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.900 ns" { clk clk~out ch:u4|sel[2] ch:u4|nod } { 0.000ns 0.000ns 4.500ns 1.200ns } { 0.000ns 3.100ns 1.100ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "21.600 ns" { clk fen:u1|cq fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "21.600 ns" { clk clk~out fen:u1|cq fen:u1|dq lock:u3|m5[1] } { 0.000ns 0.000ns 4.500ns 6.300ns 5.500ns } { 0.000ns 3.100ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 111 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.100 ns + " "Info: + Micro setup delay of destination is 4.100 ns" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 124 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 111 -1 0 } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 124 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { lock:u3|m5[1] ch:u4|Mux0~93 ch:u4|Mux0~94 ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { lock:u3|m5[1] ch:u4|Mux0~93 ch:u4|Mux0~94 ch:u4|nod } { 0.000ns 0.200ns 0.200ns 0.200ns } { 0.000ns 1.900ns 1.700ns 1.700ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.900 ns" { clk ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.900 ns" { clk clk~out ch:u4|sel[2] ch:u4|nod } { 0.000ns 0.000ns 4.500ns 1.200ns } { 0.000ns 3.100ns 1.100ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "21.600 ns" { clk fen:u1|cq fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "21.600 ns" { clk clk~out fen:u1|cq fen:u1|dq lock:u3|m5[1] } { 0.000ns 0.000ns 4.500ns 6.300ns 5.500ns } { 0.000ns 3.100ns 1.100ns 1.100ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ch:u4\|sel\[2\] ch:u4\|tmp\[0\] clk 1.9 ns " "Info: Found hold time violation between source  pin or register \"ch:u4\|sel\[2\]\" and destination pin or register \"ch:u4\|tmp\[0\]\" for clock \"clk\" (Hold time is 1.9 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.100 ns + Largest " "Info: + Largest clock skew is 8.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.700 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 15.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 14 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(1.100 ns) 8.700 ns ch:u4\|sel\[2\] 2 REG LC3_D35 8 " "Info: 2: + IC(4.500 ns) + CELL(1.100 ns) = 8.700 ns; Loc. = LC3_D35; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 11.800 ns ch:u4\|Mux6~10 3 COMB LC2_D36 4 " "Info: 3: + IC(1.100 ns) + CELL(2.000 ns) = 11.800 ns; Loc. = LC2_D36; Fanout = 4; COMB Node = 'ch:u4\|Mux6~10'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { ch:u4|sel[2] ch:u4|Mux6~10 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.900 ns) + CELL(2.000 ns) 15.700 ns ch:u4\|tmp\[0\] 4 REG LC3_D42 1 " "Info: 4: + IC(1.900 ns) + CELL(2.000 ns) = 15.700 ns; Loc. = LC3_D42; Fanout = 1; REG Node = 'ch:u4\|tmp\[0\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.900 ns" { ch:u4|Mux6~10 ch:u4|tmp[0] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.200 ns ( 52.23 % ) " "Info: Total cell delay = 8.200 ns ( 52.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 47.77 % ) " "Info: Total interconnect delay = 7.500 ns ( 47.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~10 ch:u4|tmp[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk clk~out ch:u4|sel[2] ch:u4|Mux6~10 ch:u4|tmp[0] } { 0.000ns 0.000ns 4.500ns 1.100ns 1.900ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.600 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 14 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 14; CLK Node = 'clk'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(0.000 ns) 7.600 ns ch:u4\|sel\[2\] 2 REG LC3_D35 8 " "Info: 2: + IC(4.500 ns) + CELL(0.000 ns) = 7.600 ns; Loc. = LC3_D35; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.500 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 40.79 % ) " "Info: Total cell delay = 3.100 ns ( 40.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.500 ns ( 59.21 % ) " "Info: Total interconnect delay = 4.500 ns ( 59.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { clk clk~out ch:u4|sel[2] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 3.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~10 ch:u4|tmp[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk clk~out ch:u4|sel[2] ch:u4|Mux6~10 ch:u4|tmp[0] } { 0.000ns 0.000ns 4.500ns 1.100ns 1.900ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { clk clk~out ch:u4|sel[2] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 3.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.100 ns - Shortest register register " "Info: - Shortest register to register delay is 5.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ch:u4\|sel\[2\] 1 REG LC3_D35 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_D35; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(2.000 ns) 3.200 ns ch:u4\|Mux2~14 2 COMB LC8_D42 1 " "Info: 2: + IC(1.200 ns) + CELL(2.000 ns) = 3.200 ns; Loc. = LC8_D42; Fanout = 1; COMB Node = 'ch:u4\|Mux2~14'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { ch:u4|sel[2] ch:u4|Mux2~14 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 5.100 ns ch:u4\|tmp\[0\] 3 REG LC3_D42 1 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.100 ns; Loc. = LC3_D42; Fanout = 1; REG Node = 'ch:u4\|tmp\[0\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { ch:u4|Mux2~14 ch:u4|tmp[0] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns ( 72.55 % ) " "Info: Total cell delay = 3.700 ns ( 72.55 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 27.45 % ) " "Info: Total interconnect delay = 1.400 ns ( 27.45 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { ch:u4|sel[2] ch:u4|Mux2~14 ch:u4|tmp[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.100 ns" { ch:u4|sel[2] ch:u4|Mux2~14 ch:u4|tmp[0] } { 0.000ns 1.200ns 0.200ns } { 0.000ns 2.000ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~10 ch:u4|tmp[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk clk~out ch:u4|sel[2] ch:u4|Mux6~10 ch:u4|tmp[0] } { 0.000ns 0.000ns 4.500ns 1.100ns 1.900ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.600 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "7.600 ns" { clk clk~out ch:u4|sel[2] } { 0.000ns 0.000ns 4.500ns } { 0.000ns 3.100ns 0.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.100 ns" { ch:u4|sel[2] ch:u4|Mux2~14 ch:u4|tmp[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.100 ns" { ch:u4|sel[2] ch:u4|Mux2~14 ch:u4|tmp[0] } { 0.000ns 1.200ns 0.200ns } { 0.000ns 2.000ns 1.700ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0}