prev_cmp_plj.tan.qmsg

基于vhdl 的数字频率计的设计源程序及工程文件

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sig " "Info: Assuming node \"sig\" is an undefined clock" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "sig" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "ch:u4\|Mux6~10 " "Info: Detected gated clock \"ch:u4\|Mux6~10\" as buffer" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 137 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|Mux6~10" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fen:u1\|cq " "Info: Detected ripple clock \"fen:u1\|cq\" as buffer" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 9 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "fen:u1\|cq" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ch:u4\|sel\[2\] " "Info: Detected ripple clock \"ch:u4\|sel\[2\]\" as buffer" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|sel\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ch:u4\|sel\[1\] " "Info: Detected ripple clock \"ch:u4\|sel\[1\]\" as buffer" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|sel\[1\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "ch:u4\|sel\[0\] " "Info: Detected ripple clock \"ch:u4\|sel\[0\]\" as buffer" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 132 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|sel\[0\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "fen:u1\|dq " "Info: Detected ripple clock \"fen:u1\|dq\" as buffer" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 27 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "fen:u1\|dq" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sig register pilvji:u2\|c2\[0\] register pilvji:u2\|q3\[2\] 37.88 MHz 26.4 ns Internal " "Info: Clock \"sig\" has Internal fmax of 37.88 MHz between source register \"pilvji:u2\|c2\[0\]\" and destination register \"pilvji:u2\|q3\[2\]\" (period= 26.4 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "24.600 ns + Longest register register " "Info: + Longest register to register delay is 24.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pilvji:u2\|c2\[0\] 1 REG LC2_D12 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC2_D12; Fanout = 5; REG Node = 'pilvji:u2\|c2\[0\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { pilvji:u2|c2[0] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 3.100 ns pilvji:u2\|LessThan2~23 2 COMB LC1_D11 5 " "Info: 2: + IC(1.100 ns) + CELL(2.000 ns) = 3.100 ns; Loc. = LC1_D11; Fanout = 5; COMB Node = 'pilvji:u2\|LessThan2~23'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { pilvji:u2|c2[0] pilvji:u2|LessThan2~23 } "NODE_NAME" } } { "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 6.100 ns pilvji:u2\|c6~307 3 COMB LC2_D10 10 " "Info: 3: + IC(1.100 ns) + CELL(1.900 ns) = 6.100 ns; Loc. = LC2_D10; Fanout = 10; COMB Node = 'pilvji:u2\|c6~307'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { pilvji:u2|LessThan2~23 pilvji:u2|c6~307 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 8.000 ns pilvji:u2\|c6~308 4 COMB LC1_D10 6 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 8.000 ns; Loc. = LC1_D10; Fanout = 6; COMB Node = 'pilvji:u2\|c6~308'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { pilvji:u2|c6~307 pilvji:u2|c6~308 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.900 ns) 11.000 ns pilvji:u2\|c6~309 5 COMB LC5_D9 6 " "Info: 5: + IC(1.100 ns) + CELL(1.900 ns) = 11.000 ns; Loc. = LC5_D9; Fanout = 6; COMB Node = 'pilvji:u2\|c6~309'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { pilvji:u2|c6~308 pilvji:u2|c6~309 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 13.400 ns pilvji:u2\|c6~315 6 COMB LC8_D9 1 " "Info: 6: + IC(0.200 ns) + CELL(2.200 ns) = 13.400 ns; Loc. = LC8_D9; Fanout = 1; COMB Node = 'pilvji:u2\|c6~315'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { pilvji:u2|c6~309 pilvji:u2|c6~315 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 15.600 ns pilvji:u2\|Equal0~38 7 COMB LC4_D9 23 " "Info: 7: + IC(0.200 ns) + CELL(2.000 ns) = 15.600 ns; Loc. = LC4_D9; Fanout = 23; COMB Node = 'pilvji:u2\|Equal0~38'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { pilvji:u2|c6~315 pilvji:u2|Equal0~38 } "NODE_NAME" } } { "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1871 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(1.700 ns) 18.500 ns pilvji:u2\|dian0~26 8 COMB LC1_D6 17 " "Info: 8: + IC(1.200 ns) + CELL(1.700 ns) = 18.500 ns; Loc. = LC1_D6; Fanout = 17; COMB Node = 'pilvji:u2\|dian0~26'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.900 ns" { pilvji:u2|Equal0~38 pilvji:u2|dian0~26 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 21.300 ns pilvji:u2\|q3~1262 9 COMB LC7_D3 1 " "Info: 9: + IC(1.100 ns) + CELL(1.700 ns) = 21.300 ns; Loc. = LC7_D3; Fanout = 1; COMB Node = 'pilvji:u2\|q3~1262'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { pilvji:u2|dian0~26 pilvji:u2|q3~1262 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 23.200 ns pilvji:u2\|q3~1264 10 COMB LC8_D3 1 " "Info: 10: + IC(0.200 ns) + CELL(1.700 ns) = 23.200 ns; Loc. = LC8_D3; Fanout = 1; COMB Node = 'pilvji:u2\|q3~1264'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { pilvji:u2|q3~1262 pilvji:u2|q3~1264 } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 43 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.200 ns) 24.600 ns pilvji:u2\|q3\[2\] 11 REG LC3_D3 1 " "Info: 11: + IC(0.200 ns) + CELL(1.200 ns) = 24.600 ns; Loc. = LC3_D3; Fanout = 1; REG Node = 'pilvji:u2\|q3\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { pilvji:u2|q3~1264 pilvji:u2|q3[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns ( 73.17 % ) " "Info: Total cell delay = 18.000 ns ( 73.17 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.600 ns ( 26.83 % ) " "Info: Total interconnect delay = 6.600 ns ( 26.83 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "24.600 ns" { pilvji:u2|c2[0] pilvji:u2|LessThan2~23 pilvji:u2|c6~307 pilvji:u2|c6~308 pilvji:u2|c6~309 pilvji:u2|c6~315 pilvji:u2|Equal0~38 pilvji:u2|dian0~26 pilvji:u2|q3~1262 pilvji:u2|q3~1264 pilvji:u2|q3[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "24.600 ns" { pilvji:u2|c2[0] pilvji:u2|LessThan2~23 pilvji:u2|c6~307 pilvji:u2|c6~308 pilvji:u2|c6~309 pilvji:u2|c6~315 pilvji:u2|Equal0~38 pilvji:u2|dian0~26 pilvji:u2|q3~1262 pilvji:u2|q3~1264 pilvji:u2|q3[2] } { 0.000ns 1.100ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns 1.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 2.000ns 1.900ns 1.700ns 1.900ns 2.200ns 2.000ns 1.700ns 1.700ns 1.700ns 1.200ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"sig\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns sig 1 CLK PIN_80 50 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 50; CLK Node = 'sig'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pilvji:u2\|q3\[2\] 2 REG LC3_D3 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC3_D3; Fanout = 1; REG Node = 'pilvji:u2\|q3\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { sig pilvji:u2|q3[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|q3[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig sig~out pilvji:u2|q3[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"sig\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns sig 1 CLK PIN_80 50 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 50; CLK Node = 'sig'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pilvji:u2\|c2\[0\] 2 REG LC2_D12 5 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_D12; Fanout = 5; REG Node = 'pilvji:u2\|c2\[0\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { sig pilvji:u2|c2[0] } "NODE_NAME" } } { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 50 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|c2[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig sig~out pilvji:u2|c2[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|q3[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig sig~out pilvji:u2|q3[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|c2[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig sig~out pilvji:u2|c2[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "plj.vhd" "" { Text "N:/eda/plj6/plj.vhd" 50 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "24.600 ns" { pilvji:u2|c2[0] pilvji:u2|LessThan2~23 pilvji:u2|c6~307 pilvji:u2|c6~308 pilvji:u2|c6~309 pilvji:u2|c6~315 pilvji:u2|Equal0~38 pilvji:u2|dian0~26 pilvji:u2|q3~1262 pilvji:u2|q3~1264 pilvji:u2|q3[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "24.600 ns" { pilvji:u2|c2[0] pilvji:u2|LessThan2~23 pilvji:u2|c6~307 pilvji:u2|c6~308 pilvji:u2|c6~309 pilvji:u2|c6~315 pilvji:u2|Equal0~38 pilvji:u2|dian0~26 pilvji:u2|q3~1262 pilvji:u2|q3~1264 pilvji:u2|q3[2] } { 0.000ns 1.100ns 1.100ns 0.200ns 1.100ns 0.200ns 0.200ns 1.200ns 1.100ns 0.200ns 0.200ns } { 0.000ns 2.000ns 1.900ns 1.700ns 1.900ns 2.200ns 2.000ns 1.700ns 1.700ns 1.700ns 1.200ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|q3[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig sig~out pilvji:u2|q3[2] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|c2[0] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig sig~out pilvji:u2|c2[0] } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}