plj.tan.qmsg

基于vhdl 的数字频率计的设计源程序及工程文件

{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "ch:u4\|sel\[2\] ch:u4\|tmp\[1\] clk 1.6 ns " "Info: Found hold time violation between source  pin or register \"ch:u4\|sel\[2\]\" and destination pin or register \"ch:u4\|tmp\[1\]\" for clock \"clk\" (Hold time is 1.6 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "8.300 ns + Largest " "Info: + Largest clock skew is 8.300 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 15.700 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 15.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 12 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 12; CLK Node = 'clk'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.100 ns) 8.500 ns ch:u4\|sel\[2\] 2 REG LC3_F45 8 " "Info: 2: + IC(4.300 ns) + CELL(1.100 ns) = 8.500 ns; Loc. = LC3_F45; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.400 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 11.600 ns ch:u4\|Mux6~24 3 COMB LC2_F52 4 " "Info: 3: + IC(1.100 ns) + CELL(2.000 ns) = 11.600 ns; Loc. = LC2_F52; Fanout = 4; COMB Node = 'ch:u4\|Mux6~24'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { ch:u4|sel[2] ch:u4|Mux6~24 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.000 ns) 15.700 ns ch:u4\|tmp\[1\] 4 REG LC4_F29 1 " "Info: 4: + IC(2.100 ns) + CELL(2.000 ns) = 15.700 ns; Loc. = LC4_F29; Fanout = 1; REG Node = 'ch:u4\|tmp\[1\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { ch:u4|Mux6~24 ch:u4|tmp[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.200 ns ( 52.23 % ) " "Info: Total cell delay = 8.200 ns ( 52.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 47.77 % ) " "Info: Total interconnect delay = 7.500 ns ( 47.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~24 ch:u4|tmp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|Mux6~24 {} ch:u4|tmp[1] {} } { 0.000ns 0.000ns 4.300ns 1.100ns 2.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.400 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to source register is 7.400 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 12 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 12; CLK Node = 'clk'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(0.000 ns) 7.400 ns ch:u4\|sel\[2\] 2 REG LC3_F45 8 " "Info: 2: + IC(4.300 ns) + CELL(0.000 ns) = 7.400 ns; Loc. = LC3_F45; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.100 ns ( 41.89 % ) " "Info: Total cell delay = 3.100 ns ( 41.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.300 ns ( 58.11 % ) " "Info: Total interconnect delay = 4.300 ns ( 58.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { clk {} clk~out {} ch:u4|sel[2] {} } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.100ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~24 ch:u4|tmp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|Mux6~24 {} ch:u4|tmp[1] {} } { 0.000ns 0.000ns 4.300ns 1.100ns 2.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { clk {} clk~out {} ch:u4|sel[2] {} } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.100ns 0.000ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns - " "Info: - Micro clock to output delay of source is 1.100 ns" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.600 ns - Shortest register register " "Info: - Shortest register to register delay is 5.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ch:u4\|sel\[2\] 1 REG LC3_F45 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F45; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.700 ns) + CELL(2.000 ns) 3.700 ns ch:u4\|Mux3~14 2 COMB LC8_F29 1 " "Info: 2: + IC(1.700 ns) + CELL(2.000 ns) = 3.700 ns; Loc. = LC8_F29; Fanout = 1; COMB Node = 'ch:u4\|Mux3~14'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.700 ns" { ch:u4|sel[2] ch:u4|Mux3~14 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 5.600 ns ch:u4\|tmp\[1\] 3 REG LC4_F29 1 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 5.600 ns; Loc. = LC4_F29; Fanout = 1; REG Node = 'ch:u4\|tmp\[1\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { ch:u4|Mux3~14 ch:u4|tmp[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.700 ns ( 66.07 % ) " "Info: Total cell delay = 3.700 ns ( 66.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.900 ns ( 33.93 % ) " "Info: Total interconnect delay = 1.900 ns ( 33.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { ch:u4|sel[2] ch:u4|Mux3~14 ch:u4|tmp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { ch:u4|sel[2] {} ch:u4|Mux3~14 {} ch:u4|tmp[1] {} } { 0.000ns 1.700ns 0.200ns } { 0.000ns 2.000ns 1.700ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.000 ns + " "Info: + Micro hold delay of destination is 0.000 ns" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~24 ch:u4|tmp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|Mux6~24 {} ch:u4|tmp[1] {} } { 0.000ns 0.000ns 4.300ns 1.100ns 2.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.400 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "7.400 ns" { clk {} clk~out {} ch:u4|sel[2] {} } { 0.000ns 0.000ns 4.300ns } { 0.000ns 3.100ns 0.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { ch:u4|sel[2] ch:u4|Mux3~14 ch:u4|tmp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.600 ns" { ch:u4|sel[2] {} ch:u4|Mux3~14 {} ch:u4|tmp[1] {} } { 0.000ns 1.700ns 0.200ns } { 0.000ns 2.000ns 1.700ns } "" } }  } 0 0 "Found hold time violation between source  pin or register \"%1!s!\" and destination pin or register \"%2!s!\" for clock \"%3!s!\" (Hold time is %4!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_TSU_RESULT" "pilvji:u2\|alm clr sig 3.100 ns register " "Info: tsu for register \"pilvji:u2\|alm\" (data pin = \"clr\", clock pin = \"sig\") is 3.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.300 ns + Longest pin register " "Info: + Longest pin to register delay is 4.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns clr 1 PIN PIN_182 1 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_182; Fanout = 1; PIN Node = 'clr'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clr } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.600 ns) + CELL(1.700 ns) 3.800 ns pilvji:u2\|alm~32 2 COMB LC6_F16 1 " "Info: 2: + IC(1.600 ns) + CELL(1.700 ns) = 3.800 ns; Loc. = LC6_F16; Fanout = 1; COMB Node = 'pilvji:u2\|alm~32'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.300 ns" { clr pilvji:u2|alm~32 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(0.300 ns) 4.300 ns pilvji:u2\|alm 3 REG LC8_F16 1 " "Info: 3: + IC(0.200 ns) + CELL(0.300 ns) = 4.300 ns; Loc. = LC8_F16; Fanout = 1; REG Node = 'pilvji:u2\|alm'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "0.500 ns" { pilvji:u2|alm~32 pilvji:u2|alm } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.500 ns ( 58.14 % ) " "Info: Total cell delay = 2.500 ns ( 58.14 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.800 ns ( 41.86 % ) " "Info: Total interconnect delay = 1.800 ns ( 41.86 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { clr pilvji:u2|alm~32 pilvji:u2|alm } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "4.300 ns" { clr {} clr~out {} pilvji:u2|alm~32 {} pilvji:u2|alm {} } { 0.000ns 0.000ns 1.600ns 0.200ns } { 0.000ns 0.500ns 1.700ns 0.300ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 42 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 1.900 ns - Shortest register " "Info: - Shortest clock path from clock \"sig\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns sig 1 CLK PIN_80 50 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 50; CLK Node = 'sig'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pilvji:u2\|alm 2 REG LC8_F16 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_F16; Fanout = 1; REG Node = 'pilvji:u2\|alm'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { sig pilvji:u2|alm } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|alm } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|alm {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { clr pilvji:u2|alm~32 pilvji:u2|alm } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "4.300 ns" { clr {} clr~out {} pilvji:u2|alm~32 {} pilvji:u2|alm {} } { 0.000ns 0.000ns 1.600ns 0.200ns } { 0.000ns 0.500ns 1.700ns 0.300ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|alm } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|alm {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk temp\[1\] ch:u4\|tmp\[1\] 27.200 ns register " "Info: tco from clock \"clk\" to destination pin \"temp\[1\]\" through register \"ch:u4\|tmp\[1\]\" is 27.200 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 15.700 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 15.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 12 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 12; CLK Node = 'clk'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.100 ns) 8.500 ns ch:u4\|sel\[2\] 2 REG LC3_F45 8 " "Info: 2: + IC(4.300 ns) + CELL(1.100 ns) = 8.500 ns; Loc. = LC3_F45; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.400 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 11.600 ns ch:u4\|Mux6~24 3 COMB LC2_F52 4 " "Info: 3: + IC(1.100 ns) + CELL(2.000 ns) = 11.600 ns; Loc. = LC2_F52; Fanout = 4; COMB Node = 'ch:u4\|Mux6~24'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { ch:u4|sel[2] ch:u4|Mux6~24 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 137 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.000 ns) 15.700 ns ch:u4\|tmp\[1\] 4 REG LC4_F29 1 " "Info: 4: + IC(2.100 ns) + CELL(2.000 ns) = 15.700 ns; Loc. = LC4_F29; Fanout = 1; REG Node = 'ch:u4\|tmp\[1\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.100 ns" { ch:u4|Mux6~24 ch:u4|tmp[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.200 ns ( 52.23 % ) " "Info: Total cell delay = 8.200 ns ( 52.23 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 47.77 % ) " "Info: Total interconnect delay = 7.500 ns ( 47.77 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~24 ch:u4|tmp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|Mux6~24 {} ch:u4|tmp[1] {} } { 0.000ns 0.000ns 4.300ns 1.100ns 2.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.000 ns + " "Info: + Micro clock to output delay of source is 0.000 ns" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "11.500 ns + Longest register pin " "Info: + Longest register to pin delay is 11.500 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns ch:u4\|tmp\[1\] 1 REG LC4_F29 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_F29; Fanout = 1; REG Node = 'ch:u4\|tmp\[1\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { ch:u4|tmp[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(8.600 ns) 11.500 ns temp\[1\] 2 PIN PIN_9 0 " "Info: 2: + IC(2.900 ns) + CELL(8.600 ns) = 11.500 ns; Loc. = PIN_9; Fanout = 0; PIN Node = 'temp\[1\]'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { ch:u4|tmp[1] temp[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 156 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.600 ns ( 74.78 % ) " "Info: Total cell delay = 8.600 ns ( 74.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.900 ns ( 25.22 % ) " "Info: Total interconnect delay = 2.900 ns ( 25.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { ch:u4|tmp[1] temp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { ch:u4|tmp[1] {} temp[1] {} } { 0.000ns 2.900ns } { 0.000ns 8.600ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "15.700 ns" { clk ch:u4|sel[2] ch:u4|Mux6~24 ch:u4|tmp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "15.700 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|Mux6~24 {} ch:u4|tmp[1] {} } { 0.000ns 0.000ns 4.300ns 1.100ns 2.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.500 ns" { ch:u4|tmp[1] temp[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.500 ns" { ch:u4|tmp[1] {} temp[1] {} } { 0.000ns 2.900ns } { 0.000ns 8.600ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "ITDB_TH_RESULT" "pilvji:u2\|alm clr sig -1.500 ns register " "Info: th for register \"pilvji:u2\|alm\" (data pin = \"clr\", clock pin = \"sig\") is -1.500 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 1.900 ns + Longest register " "Info: + Longest clock path from clock \"sig\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns sig 1 CLK PIN_80 50 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 50; CLK Node = 'sig'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pilvji:u2\|alm 2 REG LC8_F16 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC8_F16; Fanout = 1; REG Node = 'pilvji:u2\|alm'" {  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { sig pilvji:u2|alm } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 42 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|alm } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|alm {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TH_DELAY"