📄 plj.tan.qmsg
字号:
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "6 " "Warning: Found 6 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_GATED_CLK" "ch:u4\|Mux6~24 " "Info: Detected gated clock \"ch:u4\|Mux6~24\" as buffer" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 137 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|Mux6~24" } } } } } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fen:u1\|cq " "Info: Detected ripple clock \"fen:u1\|cq\" as buffer" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 9 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "fen:u1\|cq" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ch:u4\|sel\[2\] " "Info: Detected ripple clock \"ch:u4\|sel\[2\]\" as buffer" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|sel\[2\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ch:u4\|sel\[1\] " "Info: Detected ripple clock \"ch:u4\|sel\[1\]\" as buffer" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|sel\[1\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ch:u4\|sel\[0\] " "Info: Detected ripple clock \"ch:u4\|sel\[0\]\" as buffer" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "ch:u4\|sel\[0\]" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fen:u1\|dq " "Info: Detected ripple clock \"fen:u1\|dq\" as buffer" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 27 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "fen:u1\|dq" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "sig register pilvji:u2\|c1\[2\] register pilvji:u2\|q1\[3\] 35.09 MHz 28.5 ns Internal " "Info: Clock \"sig\" has Internal fmax of 35.09 MHz between source register \"pilvji:u2\|c1\[2\]\" and destination register \"pilvji:u2\|q1\[3\]\" (period= 28.5 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "26.700 ns + Longest register register " "Info: + Longest register to register delay is 26.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pilvji:u2\|c1\[2\] 1 REG LC1_F16 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_F16; Fanout = 3; REG Node = 'pilvji:u2\|c1\[2\]'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { pilvji:u2|c1[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 2.800 ns pilvji:u2\|LessThan1~61 2 COMB LC2_F17 11 " "Info: 2: + IC(1.100 ns) + CELL(1.700 ns) = 2.800 ns; Loc. = LC2_F17; Fanout = 11; COMB Node = 'pilvji:u2\|LessThan1~61'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { pilvji:u2|c1[2] pilvji:u2|LessThan1~61 } "NODE_NAME" } } { "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1473 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.100 ns) + CELL(2.200 ns) 7.100 ns pilvji:u2\|c6~269 3 COMB LC1_F32 10 " "Info: 3: + IC(2.100 ns) + CELL(2.200 ns) = 7.100 ns; Loc. = LC1_F32; Fanout = 10; COMB Node = 'pilvji:u2\|c6~269'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "4.300 ns" { pilvji:u2|LessThan1~61 pilvji:u2|c6~269 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(1.700 ns) 9.900 ns pilvji:u2\|c6~270 4 COMB LC3_F33 6 " "Info: 4: + IC(1.100 ns) + CELL(1.700 ns) = 9.900 ns; Loc. = LC3_F33; Fanout = 6; COMB Node = 'pilvji:u2\|c6~270'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.800 ns" { pilvji:u2|c6~269 pilvji:u2|c6~270 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 12.000 ns pilvji:u2\|c6~271 5 COMB LC7_F33 6 " "Info: 5: + IC(0.200 ns) + CELL(1.900 ns) = 12.000 ns; Loc. = LC7_F33; Fanout = 6; COMB Node = 'pilvji:u2\|c6~271'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { pilvji:u2|c6~270 pilvji:u2|c6~271 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.200 ns) 14.400 ns pilvji:u2\|c6~277 6 COMB LC8_F33 1 " "Info: 6: + IC(0.200 ns) + CELL(2.200 ns) = 14.400 ns; Loc. = LC8_F33; Fanout = 1; COMB Node = 'pilvji:u2\|c6~277'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.400 ns" { pilvji:u2|c6~271 pilvji:u2|c6~277 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(2.000 ns) 16.600 ns pilvji:u2\|Equal0~34 7 COMB LC5_F33 24 " "Info: 7: + IC(0.200 ns) + CELL(2.000 ns) = 16.600 ns; Loc. = LC5_F33; Fanout = 24; COMB Node = 'pilvji:u2\|Equal0~34'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.200 ns" { pilvji:u2|c6~277 pilvji:u2|Equal0~34 } "NODE_NAME" } } { "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "e:/software/quartus2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1871 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.900 ns) 19.800 ns pilvji:u2\|q2~556 8 COMB LC1_F38 12 " "Info: 8: + IC(1.300 ns) + CELL(1.900 ns) = 19.800 ns; Loc. = LC1_F38; Fanout = 12; COMB Node = 'pilvji:u2\|q2~556'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.200 ns" { pilvji:u2|Equal0~34 pilvji:u2|q2~556 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.300 ns) + CELL(1.700 ns) 22.800 ns pilvji:u2\|q1~557 9 COMB LC1_F47 1 " "Info: 9: + IC(1.300 ns) + CELL(1.700 ns) = 22.800 ns; Loc. = LC1_F47; Fanout = 1; COMB Node = 'pilvji:u2\|q1~557'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.000 ns" { pilvji:u2|q2~556 pilvji:u2|q1~557 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.000 ns) + CELL(1.700 ns) 25.500 ns pilvji:u2\|q1~558 10 COMB LC6_F51 1 " "Info: 10: + IC(1.000 ns) + CELL(1.700 ns) = 25.500 ns; Loc. = LC6_F51; Fanout = 1; COMB Node = 'pilvji:u2\|q1~558'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.700 ns" { pilvji:u2|q1~557 pilvji:u2|q1~558 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 43 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.000 ns) 26.700 ns pilvji:u2\|q1\[3\] 11 REG LC2_F51 1 " "Info: 11: + IC(0.200 ns) + CELL(1.000 ns) = 26.700 ns; Loc. = LC2_F51; Fanout = 1; REG Node = 'pilvji:u2\|q1\[3\]'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { pilvji:u2|q1~558 pilvji:u2|q1[3] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "18.000 ns ( 67.42 % ) " "Info: Total cell delay = 18.000 ns ( 67.42 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.700 ns ( 32.58 % ) " "Info: Total interconnect delay = 8.700 ns ( 32.58 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "26.700 ns" { pilvji:u2|c1[2] pilvji:u2|LessThan1~61 pilvji:u2|c6~269 pilvji:u2|c6~270 pilvji:u2|c6~271 pilvji:u2|c6~277 pilvji:u2|Equal0~34 pilvji:u2|q2~556 pilvji:u2|q1~557 pilvji:u2|q1~558 pilvji:u2|q1[3] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "26.700 ns" { pilvji:u2|c1[2] {} pilvji:u2|LessThan1~61 {} pilvji:u2|c6~269 {} pilvji:u2|c6~270 {} pilvji:u2|c6~271 {} pilvji:u2|c6~277 {} pilvji:u2|Equal0~34 {} pilvji:u2|q2~556 {} pilvji:u2|q1~557 {} pilvji:u2|q1~558 {} pilvji:u2|q1[3] {} } { 0.000ns 1.100ns 2.100ns 1.100ns 0.200ns 0.200ns 0.200ns 1.300ns 1.300ns 1.000ns 0.200ns } { 0.000ns 1.700ns 2.200ns 1.700ns 1.900ns 2.200ns 2.000ns 1.900ns 1.700ns 1.700ns 1.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig destination 1.900 ns + Shortest register " "Info: + Shortest clock path from clock \"sig\" to destination register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns sig 1 CLK PIN_80 50 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 50; CLK Node = 'sig'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pilvji:u2\|q1\[3\] 2 REG LC2_F51 1 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC2_F51; Fanout = 1; REG Node = 'pilvji:u2\|q1\[3\]'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { sig pilvji:u2|q1[3] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 50 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|q1[3] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|q1[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "sig source 1.900 ns - Longest register " "Info: - Longest clock path from clock \"sig\" to source register is 1.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.500 ns) 0.500 ns sig 1 CLK PIN_80 50 " "Info: 1: + IC(0.000 ns) + CELL(0.500 ns) = 0.500 ns; Loc. = PIN_80; Fanout = 50; CLK Node = 'sig'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { sig } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.400 ns) + CELL(0.000 ns) 1.900 ns pilvji:u2\|c1\[2\] 2 REG LC1_F16 3 " "Info: 2: + IC(1.400 ns) + CELL(0.000 ns) = 1.900 ns; Loc. = LC1_F16; Fanout = 3; REG Node = 'pilvji:u2\|c1\[2\]'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { sig pilvji:u2|c1[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 48 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.500 ns ( 26.32 % ) " "Info: Total cell delay = 0.500 ns ( 26.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.400 ns ( 73.68 % ) " "Info: Total interconnect delay = 1.400 ns ( 73.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|c1[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|c1[2] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|q1[3] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|q1[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|c1[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|c1[2] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 48 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.700 ns + " "Info: + Micro setup delay of destination is 0.700 ns" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 50 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "26.700 ns" { pilvji:u2|c1[2] pilvji:u2|LessThan1~61 pilvji:u2|c6~269 pilvji:u2|c6~270 pilvji:u2|c6~271 pilvji:u2|c6~277 pilvji:u2|Equal0~34 pilvji:u2|q2~556 pilvji:u2|q1~557 pilvji:u2|q1~558 pilvji:u2|q1[3] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "26.700 ns" { pilvji:u2|c1[2] {} pilvji:u2|LessThan1~61 {} pilvji:u2|c6~269 {} pilvji:u2|c6~270 {} pilvji:u2|c6~271 {} pilvji:u2|c6~277 {} pilvji:u2|Equal0~34 {} pilvji:u2|q2~556 {} pilvji:u2|q1~557 {} pilvji:u2|q1~558 {} pilvji:u2|q1[3] {} } { 0.000ns 1.100ns 2.100ns 1.100ns 0.200ns 0.200ns 0.200ns 1.300ns 1.300ns 1.000ns 0.200ns } { 0.000ns 1.700ns 2.200ns 1.700ns 1.900ns 2.200ns 2.000ns 1.900ns 1.700ns 1.700ns 1.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|q1[3] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|q1[3] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { sig pilvji:u2|c1[2] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "1.900 ns" { sig {} sig~out {} pilvji:u2|c1[2] {} } { 0.000ns 0.000ns 1.400ns } { 0.000ns 0.500ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register lock:u3\|m5\[1\] register ch:u4\|nod 25.64 MHz 39.0 ns Internal " "Info: Clock \"clk\" has Internal fmax of 25.64 MHz between source register \"lock:u3\|m5\[1\]\" and destination register \"ch:u4\|nod\" (period= 39.0 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.900 ns + Longest register register " "Info: + Longest register to register delay is 5.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lock:u3\|m5\[1\] 1 REG LC3_F49 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC3_F49; Fanout = 1; REG Node = 'lock:u3\|m5\[1\]'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lock:u3|m5[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 111 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.900 ns) 2.100 ns ch:u4\|Mux0~93 2 COMB LC4_F49 1 " "Info: 2: + IC(0.200 ns) + CELL(1.900 ns) = 2.100 ns; Loc. = LC4_F49; Fanout = 1; COMB Node = 'ch:u4\|Mux0~93'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "2.100 ns" { lock:u3|m5[1] ch:u4|Mux0~93 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 137 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 4.000 ns ch:u4\|Mux0~94 3 COMB LC5_F49 1 " "Info: 3: + IC(0.200 ns) + CELL(1.700 ns) = 4.000 ns; Loc. = LC5_F49; Fanout = 1; COMB Node = 'ch:u4\|Mux0~94'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { ch:u4|Mux0~93 ch:u4|Mux0~94 } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 137 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.200 ns) + CELL(1.700 ns) 5.900 ns ch:u4\|nod 4 REG LC7_F49 1 " "Info: 4: + IC(0.200 ns) + CELL(1.700 ns) = 5.900 ns; Loc. = LC7_F49; Fanout = 1; REG Node = 'ch:u4\|nod'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "1.900 ns" { ch:u4|Mux0~94 ch:u4|nod } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 124 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 89.83 % ) " "Info: Total cell delay = 5.300 ns ( 89.83 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.600 ns ( 10.17 % ) " "Info: Total interconnect delay = 0.600 ns ( 10.17 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { lock:u3|m5[1] ch:u4|Mux0~93 ch:u4|Mux0~94 ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { lock:u3|m5[1] {} ch:u4|Mux0~93 {} ch:u4|Mux0~94 {} ch:u4|nod {} } { 0.000ns 0.200ns 0.200ns 0.200ns } { 0.000ns 1.900ns 1.700ns 1.700ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-8.400 ns - Smallest " "Info: - Smallest clock skew is -8.400 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 11.600 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 11.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 12 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 12; CLK Node = 'clk'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.300 ns) + CELL(1.100 ns) 8.500 ns ch:u4\|sel\[2\] 2 REG LC3_F45 8 " "Info: 2: + IC(4.300 ns) + CELL(1.100 ns) = 8.500 ns; Loc. = LC3_F45; Fanout = 8; REG Node = 'ch:u4\|sel\[2\]'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.400 ns" { clk ch:u4|sel[2] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 132 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.000 ns) 11.600 ns ch:u4\|nod 3 REG LC7_F49 1 " "Info: 3: + IC(1.100 ns) + CELL(2.000 ns) = 11.600 ns; Loc. = LC7_F49; Fanout = 1; REG Node = 'ch:u4\|nod'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.100 ns" { ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 124 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "6.200 ns ( 53.45 % ) " "Info: Total cell delay = 6.200 ns ( 53.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.400 ns ( 46.55 % ) " "Info: Total interconnect delay = 5.400 ns ( 46.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { clk ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|nod {} } { 0.000ns 0.000ns 4.300ns 1.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 20.000 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 20.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns clk 1 CLK PIN_60 12 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_60; Fanout = 12; CLK Node = 'clk'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.500 ns) + CELL(1.100 ns) 8.700 ns fen:u1\|cq 2 REG LC1_C45 28 " "Info: 2: + IC(4.500 ns) + CELL(1.100 ns) = 8.700 ns; Loc. = LC1_C45; Fanout = 28; REG Node = 'fen:u1\|cq'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.600 ns" { clk fen:u1|cq } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 9 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.600 ns) + CELL(1.100 ns) 16.400 ns fen:u1\|dq 3 REG LC3_C35 65 " "Info: 3: + IC(6.600 ns) + CELL(1.100 ns) = 16.400 ns; Loc. = LC3_C35; Fanout = 65; REG Node = 'fen:u1\|dq'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "7.700 ns" { fen:u1|cq fen:u1|dq } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 27 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.600 ns) + CELL(0.000 ns) 20.000 ns lock:u3\|m5\[1\] 4 REG LC3_F49 1 " "Info: 4: + IC(3.600 ns) + CELL(0.000 ns) = 20.000 ns; Loc. = LC3_F49; Fanout = 1; REG Node = 'lock:u3\|m5\[1\]'" { } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "3.600 ns" { fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 111 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.300 ns ( 26.50 % ) " "Info: Total cell delay = 5.300 ns ( 26.50 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "14.700 ns ( 73.50 % ) " "Info: Total interconnect delay = 14.700 ns ( 73.50 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "20.000 ns" { clk fen:u1|cq fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "20.000 ns" { clk {} clk~out {} fen:u1|cq {} fen:u1|dq {} lock:u3|m5[1] {} } { 0.000ns 0.000ns 4.500ns 6.600ns 3.600ns } { 0.000ns 3.100ns 1.100ns 1.100ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { clk ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|nod {} } { 0.000ns 0.000ns 4.300ns 1.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "20.000 ns" { clk fen:u1|cq fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "20.000 ns" { clk {} clk~out {} fen:u1|cq {} fen:u1|dq {} lock:u3|m5[1] {} } { 0.000ns 0.000ns 4.500ns 6.600ns 3.600ns } { 0.000ns 3.100ns 1.100ns 1.100ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.100 ns + " "Info: + Micro clock to output delay of source is 1.100 ns" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 111 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.100 ns + " "Info: + Micro setup delay of destination is 4.100 ns" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 124 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" { } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 111 -1 0 } } { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 124 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0 "" 0 0} } { { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "5.900 ns" { lock:u3|m5[1] ch:u4|Mux0~93 ch:u4|Mux0~94 ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "5.900 ns" { lock:u3|m5[1] {} ch:u4|Mux0~93 {} ch:u4|Mux0~94 {} ch:u4|nod {} } { 0.000ns 0.200ns 0.200ns 0.200ns } { 0.000ns 1.900ns 1.700ns 1.700ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "11.600 ns" { clk ch:u4|sel[2] ch:u4|nod } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "11.600 ns" { clk {} clk~out {} ch:u4|sel[2] {} ch:u4|nod {} } { 0.000ns 0.000ns 4.300ns 1.100ns } { 0.000ns 3.100ns 1.100ns 2.000ns } "" } } { "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "e:/software/quartus2/quartus/bin/TimingClosureFloorplan.fld" "" "20.000 ns" { clk fen:u1|cq fen:u1|dq lock:u3|m5[1] } "NODE_NAME" } } { "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "e:/software/quartus2/quartus/bin/Technology_Viewer.qrui" "20.000 ns" { clk {} clk~out {} fen:u1|cq {} fen:u1|dq {} lock:u3|m5[1] {} } { 0.000ns 0.000ns 4.500ns 6.600ns 3.600ns } { 0.000ns 3.100ns 1.100ns 1.100ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "clk 4 " "Warning: Circuit may not operate. Detected 4 non-operational path(s) clocked by clock \"clk\" with clock skew larger than data delay. See Compilation Report for details." { } { } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0 "" 0 0}
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