plj.tan.qmsg

基于vhdl 的数字频率计的设计源程序及工程文件

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "" "Warning: Timing Analysis is analyzing one or more combinational loops as latches" { { "Warning" "WTDB_COMB_LATCH_NODE" "ch:u4\|nod " "Warning: Node \"ch:u4\|nod\" is a latch" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 124 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ch:u4\|tmp\[0\] " "Warning: Node \"ch:u4\|tmp\[0\]\" is a latch" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ch:u4\|tmp\[1\] " "Warning: Node \"ch:u4\|tmp\[1\]\" is a latch" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ch:u4\|tmp\[2\] " "Warning: Node \"ch:u4\|tmp\[2\]\" is a latch" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0} { "Warning" "WTDB_COMB_LATCH_NODE" "ch:u4\|tmp\[3\] " "Warning: Node \"ch:u4\|tmp\[3\]\" is a latch" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 135 -1 0 } }  } 0 0 "Node \"%1!s!\" is a latch" 0 0 "" 0 0}  } {  } 0 0 "Timing Analysis is analyzing one or more combinational loops as latches" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "sig " "Info: Assuming node \"sig\" is an undefined clock" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "sig" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "plj.vhd" "" { Text "D:/学习资料/eda/plj6/plj.vhd" 152 -1 0 } } { "e:/software/quartus2/quartus/bin/Assignment Editor.qase" "" { Assignment "e:/software/quartus2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}