plj.map.summary

基于vhdl 的数字频率计的设计源程序及工程文件

Analysis & Synthesis Status : Successful - Wed May 20 23:29:08 2009
Quartus II Version : 8.1 Build 163 10/28/2008 SJ Full Version
Revision Name : plj
Top-level Entity Name : plj
Family : ACEX1K
Total logic elements : 251
Total pins : 12
Total memory bits : 0
Total PLLs : 0