📄 plj.map.rpt
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+-----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+-----------+
; Resource ; Usage ;
+-----------------------------------+-----------+
; Total logic elements ; 251 ;
; Total combinational functions ; 229 ;
; -- Total 4-input functions ; 101 ;
; -- Total 3-input functions ; 46 ;
; -- Total 2-input functions ; 34 ;
; -- Total 1-input functions ; 48 ;
; -- Total 0-input functions ; 0 ;
; Total registers ; 118 ;
; Total logic cells in carry chains ; 46 ;
; I/O pins ; 12 ;
; Maximum fan-out node ; fen:u1|dq ;
; Maximum fan-out ; 65 ;
; Total fan-out ; 855 ;
; Average fan-out ; 3.25 ;
+-----------------------------------+-----------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------+--------------+
; |plj ; 251 (0) ; 118 ; 0 ; 12 ; 133 (0) ; 22 (0) ; 96 (0) ; 46 (0) ; 0 (0) ; |plj ; work ;
; |ch:u4| ; 23 (23) ; 3 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |plj|ch:u4 ; work ;
; |fen:u1| ; 56 (14) ; 44 ; 0 ; 0 ; 12 (12) ; 0 (0) ; 44 (2) ; 42 (0) ; 0 (0) ; |plj|fen:u1 ; work ;
; |lpm_counter:\p1:cnt[0]_rtl_2| ; 10 (0) ; 10 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (0) ; 10 (0) ; 0 (0) ; |plj|fen:u1|lpm_counter:\p1:cnt[0]_rtl_2 ; work ;
; |alt_counter_f10ke:wysi_counter| ; 10 (10) ; 10 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 10 (10) ; 10 (10) ; 0 (0) ; |plj|fen:u1|lpm_counter:\p1:cnt[0]_rtl_2|alt_counter_f10ke:wysi_counter ; work ;
; |lpm_counter:\p2:d0[0]_rtl_1| ; 32 (0) ; 32 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (0) ; 32 (0) ; 0 (0) ; |plj|fen:u1|lpm_counter:\p2:d0[0]_rtl_1 ; work ;
; |alt_counter_f10ke:wysi_counter| ; 32 (32) ; 32 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 32 (32) ; 32 (32) ; 0 (0) ; |plj|fen:u1|lpm_counter:\p2:d0[0]_rtl_1|alt_counter_f10ke:wysi_counter ; work ;
; |lock:u3| ; 21 (21) ; 21 ; 0 ; 0 ; 0 (0) ; 21 (21) ; 0 (0) ; 0 (0) ; 0 (0) ; |plj|lock:u3 ; work ;
; |pilvji:u2| ; 151 (147) ; 50 ; 0 ; 0 ; 101 (101) ; 1 (1) ; 49 (45) ; 4 (0) ; 0 (0) ; |plj|pilvji:u2 ; work ;
; |lpm_counter:c0_rtl_0| ; 4 (0) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (0) ; 4 (0) ; 0 (0) ; |plj|pilvji:u2|lpm_counter:c0_rtl_0 ; work ;
; |alt_counter_f10ke:wysi_counter| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 4 (4) ; 4 (4) ; 0 (0) ; |plj|pilvji:u2|lpm_counter:c0_rtl_0|alt_counter_f10ke:wysi_counter ; work ;
+-------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------------------------------------------------------------------+
; User-Specified and Inferred Latches ;
+----------------------------------------------------+---------------------+------------------------+
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
+----------------------------------------------------+---------------------+------------------------+
; ch:u4|nod ; ch:u4|sel[2] ; yes ;
; ch:u4|tmp[0] ; ch:u4|Mux6 ; yes ;
; ch:u4|tmp[1] ; ch:u4|Mux6 ; yes ;
; ch:u4|tmp[2] ; ch:u4|Mux6 ; yes ;
; ch:u4|tmp[3] ; ch:u4|Mux6 ; yes ;
; Number of user-specified and inferred latches = 5 ; ; ;
+----------------------------------------------------+---------------------+------------------------+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
+--------------------------------------------------------------------------------+
; Registers Removed During Synthesis ;
+---------------------------------------+----------------------------------------+
; Register name ; Reason for Removal ;
+---------------------------------------+----------------------------------------+
; pilvji:u2|dian0[0] ; Stuck at GND due to stuck port data_in ;
; pilvji:u2|dang0[3] ; Stuck at GND due to stuck port data_in ;
; lock:u3|m0[3] ; Stuck at GND due to stuck port data_in ;
; lock:u3|m5[0] ; Stuck at GND due to stuck port data_in ;
; pilvji:u2|dang0[2] ; Merged with pilvji:u2|dian0[3] ;
; lock:u3|m0[2] ; Merged with lock:u3|m5[3] ;
; Total Number of Removed Registers = 6 ; ;
+---------------------------------------+----------------------------------------+
+-----------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations ;
+--------------------+---------------------------+----------------------------------------+
; Register name ; Reason for Removal ; Registers Removed due to This Register ;
+--------------------+---------------------------+----------------------------------------+
; pilvji:u2|dian0[0] ; Stuck at GND ; lock:u3|m5[0] ;
; ; due to stuck port data_in ; ;
; pilvji:u2|dang0[3] ; Stuck at GND ; lock:u3|m0[3] ;
; ; due to stuck port data_in ; ;
+--------------------+---------------------------+----------------------------------------+
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 118 ;
; Number of registers using Synchronous Clear ; 14 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 33 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------+
; Source assignments for pilvji:u2|lpm_counter:c0_rtl_0 ;
+---------------------------+-------+------+------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+------------+
+-----------------------------------------------------------+
; Source assignments for fen:u1|lpm_counter:\p2:d0[0]_rtl_1 ;
+---------------------------+-------+------+----------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+----------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+----------------+
+------------------------------------------------------------+
; Source assignments for fen:u1|lpm_counter:\p1:cnt[0]_rtl_2 ;
+---------------------------+-------+------+-----------------+
; Assignment ; Value ; From ; To ;
+---------------------------+-------+------+-----------------+
; SUPPRESS_DA_RULE_INTERNAL ; a101 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s102 ; - ; - ;
; SUPPRESS_DA_RULE_INTERNAL ; s103 ; - ; - ;
+---------------------------+-------+------+-----------------+
+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: pilvji:u2|lpm_counter:c0_rtl_0 ;
+------------------------+-------------------+------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 4 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; ACEX1K ; Untyped ;
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