📄 plj.map.rpt
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Analysis & Synthesis report for plj
Wed May 20 23:29:08 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. User-Specified and Inferred Latches
8. Registers Removed During Synthesis
9. Removed Registers Triggering Further Register Optimizations
10. General Register Statistics
11. Source assignments for pilvji:u2|lpm_counter:c0_rtl_0
12. Source assignments for fen:u1|lpm_counter:\p2:d0[0]_rtl_1
13. Source assignments for fen:u1|lpm_counter:\p1:cnt[0]_rtl_2
14. Parameter Settings for Inferred Entity Instance: pilvji:u2|lpm_counter:c0_rtl_0
15. Parameter Settings for Inferred Entity Instance: fen:u1|lpm_counter:\p2:d0[0]_rtl_1
16. Parameter Settings for Inferred Entity Instance: fen:u1|lpm_counter:\p1:cnt[0]_rtl_2
17. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed May 20 23:29:08 2009 ;
; Quartus II Version ; 8.1 Build 163 10/28/2008 SJ Full Version ;
; Revision Name ; plj ;
; Top-level Entity Name ; plj ;
; Family ; ACEX1K ;
; Total logic elements ; 251 ;
; Total pins ; 12 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
+-----------------------------+------------------------------------------+
+-------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+----------------------------------------------------------------+----------------+---------------+
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------+----------------+---------------+
; Device ; EP1K100QC208-3 ; ;
; Top-level entity name ; plj ; plj ;
; Family name ; ACEX1K ; Stratix II ;
; Use Generated Physical Constraints File ; Off ; ;
; Use smart compilation ; Off ; Off ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique ; Area ; Area ;
; Carry Chain Length ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+----------------------------------------------------------------+----------------+---------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------+
; plj.vhd ; yes ; User VHDL File ; D:/学习资料/eda/plj6/plj.vhd ;
; lpm_counter.tdf ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/lpm_counter.tdf ;
; lpm_constant.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/lpm_constant.inc ;
; lpm_decode.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/lpm_decode.inc ;
; lpm_add_sub.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/lpm_add_sub.inc ;
; cmpconst.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/cmpconst.inc ;
; lpm_compare.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/lpm_compare.inc ;
; lpm_counter.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/lpm_counter.inc ;
; dffeea.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/dffeea.inc ;
; alt_synch_counter.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/alt_synch_counter.inc ;
; alt_synch_counter_f.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/alt_synch_counter_f.inc ;
; alt_counter_f10ke.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/alt_counter_f10ke.inc ;
; alt_counter_stratix.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/alt_counter_stratix.inc ;
; aglobal81.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/aglobal81.inc ;
; alt_counter_f10ke.tdf ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/alt_counter_f10ke.tdf ;
; flex10ke_lcell.inc ; yes ; Megafunction ; e:/software/quartus2/quartus/libraries/megafunctions/flex10ke_lcell.inc ;
+----------------------------------+-----------------+-----------------+------------------------------------------------------------------------------+
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