de2_lcm_ccd.tan.rpt

DE2 CCD数码相机源代码

; Timing Models                                         ; Preliminary        ;                 ;                         ;             ;
; Number of source nodes to report per destination node ; 10                 ;                 ;                         ;             ;
; Number of destination nodes to report                 ; 10                 ;                 ;                         ;             ;
; Number of paths to report                             ; 200                ;                 ;                         ;             ;
; Report Minimum Timing Checks                          ; Off                ;                 ;                         ;             ;
; Use Fast Timing Models                                ; Off                ;                 ;                         ;             ;
; Report IO Paths Separately                            ; Off                ;                 ;                         ;             ;
; Default hold multicycle                               ; Same As Multicycle ;                 ;                         ;             ;
; Cut paths between unrelated clock domains             ; On                 ;                 ;                         ;             ;
; Cut off read during write signal paths                ; On                 ;                 ;                         ;             ;
; Cut off feedback from I/O pins                        ; On                 ;                 ;                         ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;                 ;                         ;             ;
; Ignore Clock Settings                                 ; Off                ;                 ;                         ;             ;
; Analyze latches as synchronous elements               ; On                 ;                 ;                         ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;                 ;                         ;             ;
; Enable Clock Latency                                  ; Off                ;                 ;                         ;             ;
; Cut Timing Path                                       ; On                 ; delayed_wrptr_g ; rs_dgwp|dffpipe6|dffe7a ; dcfifo_7lb1 ;
; Cut Timing Path                                       ; On                 ; rdptr_g         ; ws_dgrp|dffpipe8|dffe9a ; dcfifo_7lb1 ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                                                                                            ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Clock Node Name                                                           ; Clock Setting Name ; Type       ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset    ; Phase offset ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -2.368 ns ;              ;
; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk1 ;                    ; PLL output ; 100.0 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_50 ; 2                     ; 1                   ; -5.368 ns ;              ;
; LCM_PLL:u0|altpll:altpll_component|_clk0                                  ;                    ; PLL output ; 18.41 MHz        ; 0.000 ns      ; 0.000 ns     ; CLOCK_27 ; 15                    ; 22                  ; -2.394 ns ;              ;
; CLOCK_50                                                                  ;                    ; User Pin   ; 50.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; CLOCK_27                                                                  ;                    ; User Pin   ; 27.0 MHz         ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
; GPIO_1[10]                                                                ;                    ; User Pin   ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A       ;              ;
+---------------------------------------------------------------------------+--------------------+------------+------------------+---------------+--------------+----------+-----------------------+---------------------+-----------+--------------+


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