de2_lcm_ccd.tan.rpt

来自「DE2 CCD数码相机源代码」· RPT 代码 · 共 179 行 · 第 1/5 页

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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Type                                                                                     ; Slack     ; Required Time                     ; Actual Time                      ; From                                                                                                                         ; To                                                                                                                                                           ; From Clock                                                                ; To Clock                                                                  ; Failed Paths ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+
; Worst-case tsu                                                                           ; N/A       ; None                              ; 6.688 ns                         ; DRAM_DQ[13]                                                                                                                  ; Sdram_Control_4Port:u6|mDATAOUT[13]                                                                                                                          ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Worst-case tco                                                                           ; N/A       ; None                              ; 16.141 ns                        ; I2C_AV_Config:u9|I2C_Controller:u0|SD_COUNTER[1]~reg0                                                                        ; I2C_SCLK                                                                                                                                                     ; CLOCK_50                                                                  ; --                                                                        ; 0            ;
; Worst-case tpd                                                                           ; N/A       ; None                              ; 10.553 ns                        ; SW[14]                                                                                                                       ; LEDR[14]                                                                                                                                                     ; --                                                                        ; --                                                                        ; 0            ;
; Worst-case th                                                                            ; N/A       ; None                              ; 4.532 ns                         ; SW[0]                                                                                                                        ; I2C_CCD_Config:u7|mI2C_DATA[0]                                                                                                                               ; --                                                                        ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0' ; 2.257 ns  ; 100.00 MHz ( period = 10.000 ns ) ; 129.15 MHz ( period = 7.743 ns ) ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4] ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                                              ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'CLOCK_50'                                                                  ; 6.676 ns  ; 50.00 MHz ( period = 20.000 ns )  ; 150.42 MHz ( period = 6.648 ns ) ; I2S_LCM_Config:u8|mI2S_DATA[12]                                                                                              ; I2S_LCM_Config:u8|I2S_Controller:u0|mSDATA                                                                                                                   ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'                                  ; 48.026 ns ; 18.41 MHz ( period = 54.320 ns )  ; 158.88 MHz ( period = 6.294 ns ) ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|rdptr_g[8]                   ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|a_graycounter_g86:rdptr_g1p|power_modified_counter_values[8] ; LCM_PLL:u0|altpll:altpll_component|_clk0                                  ; LCM_PLL:u0|altpll:altpll_component|_clk0                                  ; 0            ;
; Clock Setup: 'GPIO_1[10]'                                                                ; N/A       ; None                              ; 184.03 MHz ( period = 5.434 ns ) ; CCD_Capture:u3|X_Cont[0]                                                                                                     ; RAW2RGB:u4|mCCD_G[10]                                                                                                                                        ; GPIO_1[10]                                                                ; GPIO_1[10]                                                                ; 0            ;
; Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'  ; 0.391 ns  ; 100.00 MHz ( period = 10.000 ns ) ; N/A                              ; Sdram_Control_4Port:u6|ST[0]                                                                                                 ; Sdram_Control_4Port:u6|ST[0]                                                                                                                                 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 0            ;
; Clock Hold: 'LCM_PLL:u0|altpll:altpll_component|_clk0'                                   ; 0.391 ns  ; 18.41 MHz ( period = 54.320 ns )  ; N/A                              ; LCM_Controller:u1|MOD_3[0]                                                                                                   ; LCM_Controller:u1|MOD_3[0]                                                                                                                                   ; LCM_PLL:u0|altpll:altpll_component|_clk0                                  ; LCM_PLL:u0|altpll:altpll_component|_clk0                                  ; 0            ;
; Clock Hold: 'CLOCK_50'                                                                   ; 0.391 ns  ; 50.00 MHz ( period = 20.000 ns )  ; N/A                              ; Reset_Delay:u2|oRST_1                                                                                                        ; Reset_Delay:u2|oRST_1                                                                                                                                        ; CLOCK_50                                                                  ; CLOCK_50                                                                  ; 0            ;
; Total number of failed paths                                                             ;           ;                                   ;                                  ;                                                                                                                              ;                                                                                                                                                              ;                                                                           ;                                                                           ; 0            ;
+------------------------------------------------------------------------------------------+-----------+-----------------------------------+----------------------------------+------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------+---------------------------------------------------------------------------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                             ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Option                                                ; Setting            ; From            ; To                      ; Entity Name ;
+-------------------------------------------------------+--------------------+-----------------+-------------------------+-------------+
; Device Name                                           ; EP2C35F672C6       ;                 ;                         ;             ;