de2_lcm_ccd.tan.rpt

来自「DE2 CCD数码相机源代码」· RPT 代码 · 共 179 行 · 第 1/5 页

; 2.696 ns                                ; 136.91 MHz ( period = 7.304 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]                              ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.068 ns                ;
; 2.696 ns                                ; 136.91 MHz ( period = 7.304 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]                              ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.068 ns                ;
; 2.696 ns                                ; 136.91 MHz ( period = 7.304 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[4]                              ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.068 ns                ;
; 2.707 ns                                ; 137.12 MHz ( period = 7.293 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]                              ; Sdram_Control_4Port:u6|mWR                                                                                                                                   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 7.054 ns                ;
; 2.707 ns                                ; 137.12 MHz ( period = 7.293 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]                              ; Sdram_Control_4Port:u6|WR_MASK[0]                                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 7.054 ns                ;
; 2.707 ns                                ; 137.12 MHz ( period = 7.293 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]                              ; Sdram_Control_4Port:u6|WR_MASK[1]                                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 7.054 ns                ;
; 2.708 ns                                ; 137.14 MHz ( period = 7.292 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]                              ; Sdram_Control_4Port:u6|mRD                                                                                                                                   ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 7.053 ns                ;
; 2.708 ns                                ; 137.14 MHz ( period = 7.292 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]                              ; Sdram_Control_4Port:u6|RD_MASK[0]                                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 7.053 ns                ;
; 2.708 ns                                ; 137.14 MHz ( period = 7.292 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[4]                              ; Sdram_Control_4Port:u6|RD_MASK[1]                                                                                                                            ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.761 ns                  ; 7.053 ns                ;
; 2.713 ns                                ; 137.23 MHz ( period = 7.287 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                                              ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.051 ns                ;
; 2.713 ns                                ; 137.23 MHz ( period = 7.287 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                                              ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.051 ns                ;
; 2.713 ns                                ; 137.23 MHz ( period = 7.287 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.051 ns                ;
; 2.713 ns                                ; 137.23 MHz ( period = 7.287 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.051 ns                ;
; 2.713 ns                                ; 137.23 MHz ( period = 7.287 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.764 ns                  ; 7.051 ns                ;
; 2.739 ns                                ; 137.72 MHz ( period = 7.261 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                                              ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 7.018 ns                ;
; 2.739 ns                                ; 137.72 MHz ( period = 7.261 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                                              ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 7.018 ns                ;
; 2.739 ns                                ; 137.72 MHz ( period = 7.261 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 7.018 ns                ;
; 2.739 ns                                ; 137.72 MHz ( period = 7.261 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 7.018 ns                ;
; 2.739 ns                                ; 137.72 MHz ( period = 7.261 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo2|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_bwp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.757 ns                  ; 7.018 ns                ;
; 2.747 ns                                ; 137.87 MHz ( period = 7.253 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1]                              ; Sdram_Control_4Port:u6|mADDR[8]                                                                                                                              ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 7.015 ns                ;
; 2.747 ns                                ; 137.87 MHz ( period = 7.253 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1]                              ; Sdram_Control_4Port:u6|mADDR[9]                                                                                                                              ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 7.015 ns                ;
; 2.747 ns                                ; 137.87 MHz ( period = 7.253 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1]                              ; Sdram_Control_4Port:u6|mADDR[10]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 7.015 ns                ;
; 2.747 ns                                ; 137.87 MHz ( period = 7.253 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1]                              ; Sdram_Control_4Port:u6|mADDR[11]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 7.015 ns                ;
; 2.747 ns                                ; 137.87 MHz ( period = 7.253 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[1]                              ; Sdram_Control_4Port:u6|mADDR[12]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.762 ns                  ; 7.015 ns                ;
; 2.784 ns                                ; 138.58 MHz ( period = 7.216 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]                              ; Sdram_Control_4Port:u6|mADDR[22]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.759 ns                  ; 6.975 ns                ;
; 2.785 ns                                ; 138.60 MHz ( period = 7.215 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]                              ; Sdram_Control_4Port:u6|mADDR[21]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.763 ns                  ; 6.978 ns                ;
; 2.805 ns                                ; 138.99 MHz ( period = 7.195 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[16]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.795 ns                  ; 6.990 ns                ;
; 2.805 ns                                ; 138.99 MHz ( period = 7.195 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[17]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.795 ns                  ; 6.990 ns                ;
; 2.805 ns                                ; 138.99 MHz ( period = 7.195 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[18]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.795 ns                  ; 6.990 ns                ;
; 2.805 ns                                ; 138.99 MHz ( period = 7.195 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[19]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.795 ns                  ; 6.990 ns                ;
; 2.805 ns                                ; 138.99 MHz ( period = 7.195 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[3]                              ; Sdram_Control_4Port:u6|mADDR[20]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.795 ns                  ; 6.990 ns                ;
; 2.812 ns                                ; 139.12 MHz ( period = 7.188 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]                              ; Sdram_Control_4Port:u6|mADDR[13]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.766 ns                  ; 6.954 ns                ;
; 2.812 ns                                ; 139.12 MHz ( period = 7.188 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]                              ; Sdram_Control_4Port:u6|mADDR[14]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.766 ns                  ; 6.954 ns                ;
; 2.812 ns                                ; 139.12 MHz ( period = 7.188 ns )                    ; Sdram_Control_4Port:u6|Sdram_FIFO:read_fifo1|dcfifo:dcfifo_component|dcfifo_7lb1:auto_generated|dffpipe_gd9:ws_brp|dffe5a[2]                              ; Sdram_Control_4Port:u6|mADDR[15]                                                                                                                             ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0 ; 10.000 ns                   ; 9.766 ns                  ; 6.954 ns                ;
; 2.8