📄 de2_lcm_ccd.tan.rpt
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Timing Analyzer report for DE2_LCM_CCD
Tue Apr 04 19:37:11 2006
Version 5.1 Build 213 01/19/2006 Service Pack 1 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
6. Clock Setup: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
7. Clock Setup: 'CLOCK_50'
8. Clock Setup: 'GPIO_1[10]'
9. Clock Hold: 'Sdram_Control_4Port:u6|Sdram_PLL:sdram_pll1|altpll:altpll_component|_clk0'
10. Clock Hold: 'LCM_PLL:u0|altpll:altpll_component|_clk0'
11. Clock Hold: 'CLOCK_50'
12. tsu
13. tco
14. tpd
15. th
16. Timing Analyzer Messages
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; Legal Notice ;
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Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
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