fadd.vhd

基于VHDL语言的32位单精度的浮点加法器

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM "Quartus II"
-- VERSION "Version 5.1 Build 176 10/26/2005 SJ Full Version"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY FADD IS 
	port
	(
		X :  IN  STD_LOGIC_VECTOR(31 downto 0);
		Y :  IN  STD_LOGIC_VECTOR(31 downto 0);
		FZERO :  OUT  STD_LOGIC;
		FUNDF :  OUT  STD_LOGIC;
		FOVF :  OUT  STD_LOGIC;
		BIGMAN :  OUT  STD_LOGIC_VECTOR(24 downto 0);
		RESULT :  OUT  STD_LOGIC_VECTOR(31 downto 0)
	);
END FADD;

ARCHITECTURE bdf_type OF FADD IS 

component adjust
	PORT(XSIGN : IN STD_LOGIC;
		 YSIGN : IN STD_LOGIC;
		 BIGEXP : IN STD_LOGIC_VECTOR(7 downto 0);
		 MANSFT : IN STD_LOGIC_VECTOR(24 downto 0);
		 MANSUM : IN STD_LOGIC_VECTOR(25 downto 0);
		 SHIFTK : IN STD_LOGIC_VECTOR(4 downto 0);
		 FOVF : OUT STD_LOGIC;
		 FUNDF : OUT STD_LOGIC;
		 FZERO : OUT STD_LOGIC;
		 RESULT : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component barrelr
	PORT(SIGN : IN STD_LOGIC;
		 IN0 : IN STD_LOGIC_VECTOR(31 downto 0);
		 S : IN STD_LOGIC_VECTOR(4 downto 0);
		 Y : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component ext_32to25
	PORT(RIGHTOUT : IN STD_LOGIC_VECTOR(31 downto 0);
		 SMALLMAN : OUT STD_LOGIC_VECTOR(24 downto 0)
	);
end component;

component expcomp
	PORT(XEXP : IN STD_LOGIC_VECTOR(7 downto 0);
		 YEXP : IN STD_LOGIC_VECTOR(7 downto 0);
		 BIGX : OUT STD_LOGIC;
		 TOOSMALL : OUT STD_LOGIC;
		 BIGEXP : OUT STD_LOGIC_VECTOR(7 downto 0);
		 SHIFTD : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

component leadsign
	PORT(DIN : IN STD_LOGIC_VECTOR(24 downto 0);
		 CNT : OUT STD_LOGIC_VECTOR(4 downto 0)
	);
end component;

component manadd
	PORT(BIGMAN : IN STD_LOGIC_VECTOR(24 downto 0);
		 SMALLMAN : IN STD_LOGIC_VECTOR(24 downto 0);
		 MANSUM : OUT STD_LOGIC_VECTOR(25 downto 0)
	);
end component;

component manmux
	PORT(BIGX : IN STD_LOGIC;
		 TOOSMALL : IN STD_LOGIC;
		 X : IN STD_LOGIC_VECTOR(31 downto 0);
		 Y : IN STD_LOGIC_VECTOR(31 downto 0);
		 BIGMAN : OUT STD_LOGIC_VECTOR(24 downto 0);
		 TOSHIFT : OUT STD_LOGIC_VECTOR(24 downto 0)
	);
end component;

component barrell
	PORT(IN0 : IN STD_LOGIC_VECTOR(31 downto 0);
		 S : IN STD_LOGIC_VECTOR(4 downto 0);
		 Y : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component ext2_25to32
	PORT(MANSUM25 : IN STD_LOGIC_VECTOR(24 downto 0);
		 LEFTDIN : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

component ext2_32to25
	PORT(LEFTOUT : IN STD_LOGIC_VECTOR(31 downto 0);
		 MANSFT : OUT STD_LOGIC_VECTOR(24 downto 0)
	);
end component;

component ext_25to32
	PORT(TOSHIFT : IN STD_LOGIC_VECTOR(24 downto 0);
		 RIGHTDIN : OUT STD_LOGIC_VECTOR(31 downto 0)
	);
end component;

signal	MANSUM :  STD_LOGIC_VECTOR(25 downto 0);
signal	TOSHIFT :  STD_LOGIC_VECTOR(24 downto 0);
signal	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(7 downto 0);
signal	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(24 downto 0);
signal	SYNTHESIZED_WIRE_13 :  STD_LOGIC_VECTOR(4 downto 0);
signal	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(4 downto 0);
signal	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(24 downto 0);
signal	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(24 downto 0);
signal	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
signal	SYNTHESIZED_WIRE_10 :  STD_LOGIC_VECTOR(31 downto 0);
signal	SYNTHESIZED_WIRE_12 :  STD_LOGIC_VECTOR(31 downto 0);


BEGIN 
BIGMAN <= SYNTHESIZED_WIRE_6;



b2v_inst : adjust
PORT MAP(XSIGN => X(23),
		 YSIGN => Y(23),
		 BIGEXP => SYNTHESIZED_WIRE_0,
		 MANSFT => SYNTHESIZED_WIRE_1,
		 MANSUM => MANSUM,
		 SHIFTK => SYNTHESIZED_WIRE_13,
		 FOVF => FOVF,
		 FUNDF => FUNDF,
		 FZERO => FZERO,
		 RESULT => RESULT);

b2v_inst1 : barrelr
PORT MAP(SIGN => TOSHIFT(24),
		 IN0 => SYNTHESIZED_WIRE_3,
		 S => SYNTHESIZED_WIRE_4,
		 Y => SYNTHESIZED_WIRE_5);

b2v_inst10 : ext_32to25
PORT MAP(RIGHTOUT => SYNTHESIZED_WIRE_5,
		 SMALLMAN => SYNTHESIZED_WIRE_7);

b2v_inst2 : expcomp
PORT MAP(XEXP => X(31 downto 24),
		 YEXP => Y(31 downto 24),
		 BIGX => SYNTHESIZED_WIRE_8,
		 TOOSMALL => SYNTHESIZED_WIRE_9,
		 BIGEXP => SYNTHESIZED_WIRE_0,
		 SHIFTD => SYNTHESIZED_WIRE_4);

b2v_inst3 : leadsign
PORT MAP(DIN => MANSUM(24 downto 0),
		 CNT => SYNTHESIZED_WIRE_13);

b2v_inst4 : manadd
PORT MAP(BIGMAN => SYNTHESIZED_WIRE_6,
		 SMALLMAN => SYNTHESIZED_WIRE_7,
		 MANSUM => MANSUM);

b2v_inst5 : manmux
PORT MAP(BIGX => SYNTHESIZED_WIRE_8,
		 TOOSMALL => SYNTHESIZED_WIRE_9,
		 X => X,
		 Y => Y,
		 BIGMAN => SYNTHESIZED_WIRE_6,
		 TOSHIFT => TOSHIFT);

b2v_inst6 : barrell
PORT MAP(IN0 => SYNTHESIZED_WIRE_10,
		 S => SYNTHESIZED_WIRE_13,
		 Y => SYNTHESIZED_WIRE_12);

b2v_inst7 : ext2_25to32
PORT MAP(MANSUM25 => MANSUM(24 downto 0),
		 LEFTDIN => SYNTHESIZED_WIRE_10);

b2v_inst8 : ext2_32to25
PORT MAP(LEFTOUT => SYNTHESIZED_WIRE_12,
		 MANSFT => SYNTHESIZED_WIRE_1);

b2v_inst9 : ext_25to32
PORT MAP(TOSHIFT => TOSHIFT,
		 RIGHTDIN => SYNTHESIZED_WIRE_3);

END;