adjust.vhd

基于VHDL语言的32位单精度的浮点加法器

Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity ADJUST is
    port (
        MANSUM: in std_logic_vector (25 downto 0);
        MANSFT: in std_logic_vector (24 downto 0);
        SHIFTK: in std_logic_vector (4 downto 0);
        BIGEXP: in std_logic_vector (7 downto 0);
        XSIGN : in std_logic;
        YSIGN : in std_logic;
        FOVF : out std_logic;
        FUNDF: out std_logic;
        FZERO: out std_logic;
        RESULT:  out std_logic_vector (31 downto 0)
         );
end ADJUST;

architecture RTL of ADJUST is
constant ZERO25 : std_logic_vector (24 downto 0) := (others => '0');
signal MANOVF, MANZERO : std_logic;
signal EXPOVF, EXPUNDF : std_logic;

begin

MANOVF <= '1' when (XSIGN = YSIGN) and (XSIGN /= MANSUM(24)) else '0';
MANZERO <= '1' when MANSUM(24 downto 0) = ZERO25 else '0';

expgen : process (BIGEXP, MANOVF, MANZERO, SHIFTK, XSIGN, MANSFT, MANSUM)
variable EXPADJ : std_logic_vector (7 downto 0);
begin

FOVF <= '0'; FUNDF <= '0'; FZERO <= '0';

if (MANOVF = '1') then
   EXPADJ := BIGEXP + 1;
  if (BIGEXP = "01111111") then
     FOVF <= '1';
     if (XSIGN = '0') then
        RESULT <= "01111111" & "01111111" & "11111111" & "11111111";
     else
        RESULT <= "01111111" & "10000000" & "00000000" & "00000000";        
     end if;
  else
     RESULT <= EXPADJ & MANSUM(25) & MANSUM(23 downto 1);
  end if;
elsif (MANZERO = '1') then
  RESULT <= "10000000" & ZERO25 (23 downto 0);
  FZERO <= '1';
else
  EXPADJ := BIGEXP - ("000" & SHIFTK);
   if (BIGEXP(7) = '1') and (EXPADJ(7) = '0') then
     RESULT <= "10000000" & ZERO25 (23 downto 0);
     FUNDF <= '1'; 
     FZERO <= '1';
   else
     RESULT <= EXPADJ & MANSFT(24) & MANSFT(22 downto 0);
   end if;
end if;
end process;
end RTL;