leadsign.vhd

基于VHDL语言的32位单精度的浮点加法器

Library IEEE;
use IEEE.std_logic_1164.all;

entity LEADSIGN is
    port (
        DIN : in std_logic_vector(24 downto 0);
        CNT : out std_logic_vector(4 downto 0)
         );
end LEADSIGN;

architecture RTL of LEADSIGN is

begin

p0 : process (DIN)
     variable NUM : std_logic_vector(4 downto 0);
     variable Cin, Cout : std_logic;
begin
     NUM := (others => '0');
     for j in 23 downto 0 loop
          if (DIN(j) = DIN(24)) then 
               Cin := '1';
               for k in 0 to 4 loop
                      Cout    := NUM(k) and Cin;
                      Num(k)  := NUM(k) xor Cin;
                      Cin     := Cout;
               end loop;
           else
               exit;
           end if;
      end loop;
      CNT <= NUM;
    end process;
end RTL;