ext_25to32.vhd

基于VHDL语言的32位单精度的浮点加法器

Library IEEE;
use IEEE.std_logic_1164.all;

entity EXT_25to32 is
    port (
        TOSHIFT: in std_logic_vector (24 downto 0);
        RIGHTDIN  : out std_logic_vector (31 downto 0)
         );
end EXT_25to32;

architecture RTL of EXT_25to32 is

begin

RIGHTDIN <= TOSHIFT & "0000000";

end RTL;