ext_32to25.vhd

来自「基于VHDL语言的32位单精度的浮点加法器」· VHDL 代码 · 共 17 行

Library IEEE;
use IEEE.std_logic_1164.all;

entity EXT_32to25 is
    port (
        RIGHTOUT: in std_logic_vector (31 downto 0);
        SMALLMAN: out std_logic_vector (24 downto 0)
         );
end EXT_32to25;

architecture RTL of EXT_32to25 is

begin

SMALLMAN <= RIGHTOUT (31 downto 7);

end RTL;