clock.map.summary

来自「用VHDL实现的完整数字钟代码」· SUMMARY 代码 · 共 9 行

Analysis & Synthesis Status : Successful - Thu Dec 04 16:54:40 2008
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Web Edition
Revision Name : clock
Top-level Entity Name : clock
Family : FLEX10K
Total logic elements : 86
Total pins : 19
Total memory bits : 0